Abstract
Major advances in semiconductor technologies have made possible ICs under 0.3 micron technology. As a result of these shrinking geometries, net delay is fast becoming a major component of path delays. Hence, it is essential that synthesis tools take into consideration information provided by tools used downstream in the design flow like floor-planners and place and route tools. This chapter discusses the links from and to DC and backend tools like floorplanners and place and route tools.
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Synopsys Links-to-Layout Methodology Flow Application Note
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© 1997 Kluwer Academic Publishers
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Kurup, P., Abbasi, T. (1997). Links to Layout. In: Logic Synthesis Using Synopsys®. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1455-4_6
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DOI: https://doi.org/10.1007/978-1-4613-1455-4_6
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4612-8634-9
Online ISBN: 978-1-4613-1455-4
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