Constraining and Optimizing Designs — I

Abstract

This chapter is the first of two chapters that outlines the methodology for logic synthesis using the Synopsys Design Compiler. After a design has been described in HDL and functionally simulated, the next step involves logic synthesis using DC. Herein lies the core of the synthesis process. How can one get the best results from the synthesis tool? What is the methodology to be followed in optimizing a design? Is synthesis a push-button solution? This chapter begins with a description of the constraints specified on designs and the timing reports generated by DC. A brief description of commonly used DC commands and options has been provided to help the reader get familiar with the process of optimizing designs. Then, strategies for optimization and general guidelines for synthesis are discussed. Finally, a number of “classic scenarios” have been presented based on actual user experiences. At each stage, the relevant dc_shell commands have been provided.