VHDL/Verilog Coding for Synthesis

Abstract

This chapter provides several examples of coding for synthesis in both VHDL and Verilog. First, general HDL coding issues are discussed, followed by a brief comparison of the two commonly used languages VHDL and Verilog. Then, coding for finite state machines has been discussed in detail with several examples followed by specific tips for FSM coding. Examples in both VHDL and Verilog have been provided to infer a multi-bit register, barrel shifter, incrementor etc. Finally, a few classic scenarios have been discussed.