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Low-Power CMOS ΣΔ modulators for speech coding

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Analog Circuit Design

Abstract

A ΣΔ modulator with continuous-time loopfilter has some important advantages compared to its discrete-time counterpart. Bandwidth requirements to the active elements of the loopfilter are relaxed, so that power consumption is reduced. Furthermore, aliasing is reduced, eliminating the need for an anti-aliasing filter at the modulator input. A 4th order, 64 times oversampling ΣΔ modulator with microphone input was designed and shows 80 dB dynamic range over the 300–3400 Hz voice bandwidth. THD is −72dB for a 40mVRMS maximum input signal at 95 μA current consumption from a 2.2V supply voltage. The active die area of the modulator is 0.5 mm2 in a standard 0.5μm CMOS process.

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© 2001 Kluwer Academic Publishers

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van der Zwan, E. (2001). Low-Power CMOS ΣΔ modulators for speech coding. In: Sansen, W., van de Plassche, R.J., Huijsing, J.H. (eds) Analog Circuit Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1443-1_7

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  • DOI: https://doi.org/10.1007/978-1-4613-1443-1_7

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4612-8628-8

  • Online ISBN: 978-1-4613-1443-1

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