Abstract
Application Specific Integrated Circuits (ASICs) have kept pace pace with the increasing complexity of applications and their demands for higher data rates, though this situation seems ready to change. Estimates show that the capability (in terms of gates) to design efficiently would lag considerably behind the capability to manufacture ASICs. New factors that influence the design of ASICs are also to be taken into consideration. These include; deep submicron designs, developments in synthesis and top-down design using hardware description languages (HDLs), and increasing time-to-market pressures. The primary goal is to provide users with desirable features such as — flexibility, ease-of-use, high reuse, quick-turnaround, high performance, integrability, accuracy, portability, and reliability. Existing design methodologies and environments support a few of these desirable features (see section 2.3). The purpose of this monograph was to define a design methodology for ASSPs that provides a competitive advantage to an organization through the use of commercial-off-the shelf (COTS) CAD/ESDA design environments.
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© 1996 Kluwer Academic Publishers
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Romdhane, M.S.B., Madisetti, V.K., Hines, J.W. (1996). Conclusions. In: Romdhane, M.S.B., Madisetti, V.K., Hines, J.W. (eds) Quick-Turnaround ASIC Design in VHDL. The Kluwer International Series in Engineering and Computer Science, vol 367. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1411-0_7
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DOI: https://doi.org/10.1007/978-1-4613-1411-0_7
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4612-8612-7
Online ISBN: 978-1-4613-1411-0
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