Abstract
Most ASICs fail within the board-level environment if the component interface clock-level timing and functionality is not considered early in the design process. Recent AT&T studies show that nearly 50% of ASICs fail at the system level. This chapter describes how core-based ASICs can be integrated into board-level designs.
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© 1996 Kluwer Academic Publishers
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Romdhane, M.S.B., Madisetti, V.K., Hines, J.W. (1996). Board Integration. In: Romdhane, M.S.B., Madisetti, V.K., Hines, J.W. (eds) Quick-Turnaround ASIC Design in VHDL. The Kluwer International Series in Engineering and Computer Science, vol 367. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1411-0_6
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DOI: https://doi.org/10.1007/978-1-4613-1411-0_6
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4612-8612-7
Online ISBN: 978-1-4613-1411-0
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