VHDL-Based Design

  • Mohamed S. Ben Romdhane
  • Vijay K. Madisetti
  • John W. Hines
Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 367)


Hardware design has recently undergone dramatic changes in design methodologies, especially with the proliferation of hardware description languages (HDLs) that promote the integration of the design methodology into a unified environment. Designs described in HDLs are kept at a more abstract level of representation than what traditional methods allow. HDL descriptions can take a variety of abstraction levels (See Figure 2.1). Synthesis is the step taken to translate the HDL description to a lower level of representation (i.e., the gate-level). Behavioral synthesis extracts an RTL (clock-level) structure from a behavioral HDL description. Practical approaches to behavioral synthesis set design restrictions (i.e., the use of pragmas in Mistral 2) in order to provide acceptable performance. While several HDLs exist, we recommend VHDL, which is also an IEEE standard (1076–1987/93).


Finite State Machine Nand Gate Hardware Description Language Parameter Passing VHDL Code 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Kluwer Academic Publishers 1996

Authors and Affiliations

  • Mohamed S. Ben Romdhane
    • 1
  • Vijay K. Madisetti
    • 2
  • John W. Hines
    • 3
  1. 1.Rockwell International CorporationUSA
  2. 2.Georgia Institute of Technology & VP TechnologiesUSA
  3. 3.US Air Force Wright LaboratoriesUSA

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