Hardware design has recently undergone dramatic changes in design methodologies, especially with the proliferation of hardware description languages (HDLs) that promote the integration of the design methodology into a unified environment. Designs described in HDLs are kept at a more abstract level of representation than what traditional methods allow. HDL descriptions can take a variety of abstraction levels (See Figure 2.1). Synthesis is the step taken to translate the HDL description to a lower level of representation (i.e., the gate-level). Behavioral synthesis extracts an RTL (clock-level) structure from a behavioral HDL description. Practical approaches to behavioral synthesis set design restrictions (i.e., the use of pragmas in Mistral 2) in order to provide acceptable performance. While several HDLs exist, we recommend VHDL, which is also an IEEE standard (1076–1987/93).
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