Abstract
This chapter reviews the background required for this monograph. First, common ASIC design approaches are introduced. Advantages and limitations of ASICs with regard to general-purpose DSP processors are outlined. Section 2.2 describes popular design approaches and environments proposed in recent literature to synthesize ASICs form HDL descriptions. In section 2.3, a comparison between existing ASIC design tools is proposed based on criteria such as — design turnaround, flexibility, ease-of-use, and performance. Section 2.4 introduces a cost model originally proposed by Synopsys and Xilinx that compares the ASIC and FPGA alternatives. This cost model and assumptions made will serve us later, when we compare our proposed design methodology with other high-level approaches.
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© 1996 Kluwer Academic Publishers
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Romdhane, M.S.B., Madisetti, V.K., Hines, J.W. (1996). Background. In: Romdhane, M.S.B., Madisetti, V.K., Hines, J.W. (eds) Quick-Turnaround ASIC Design in VHDL. The Kluwer International Series in Engineering and Computer Science, vol 367. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1411-0_2
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DOI: https://doi.org/10.1007/978-1-4613-1411-0_2
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4612-8612-7
Online ISBN: 978-1-4613-1411-0
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