Hierarchical Fault Modeling for Linear Analog Circuits

Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 364)


This paper presents a hierarchical fault modeling approach for catastrophic as well as out-of-specification (parametric) faults in analog circuits. These include both, ac and dc faults in passive as well as active components. The fault models are based on functional error characterization. Case studies based on CMOS and nMOS operational amplifiers are discussed, and a full listing of derived behavioral fault models is presented. These fault models are then mapped to the faulty behavior at the macro-circuit level. Application of these fault models in an efficient fault simulator for analog circuits is also described.


Fault Model Analog Circuit Fault Injection Fault Simulation Circuit Level 
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Copyright information

© Kluwer Academic Publishers, Boston 1996

Authors and Affiliations

  1. 1.LogicVisionSan JoseUSA
  2. 2.Computer Engineering Research CenterUniversity of Texas at AustinAustinUSA

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