Hierarchical Fault Modeling for Linear Analog Circuits

  • Naveena Nagi
  • Jacob A. Abraham
Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 364)

Abstract

This paper presents a hierarchical fault modeling approach for catastrophic as well as out-of-specification (parametric) faults in analog circuits. These include both, ac and dc faults in passive as well as active components. The fault models are based on functional error characterization. Case studies based on CMOS and nMOS operational amplifiers are discussed, and a full listing of derived behavioral fault models is presented. These fault models are then mapped to the faulty behavior at the macro-circuit level. Application of these fault models in an efficient fault simulator for analog circuits is also described.

Keywords

Compaction Aliasing Jood 

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References

  1. 1.
    P. M. Lin and Y. S. Elcherif, “Analogue circuits fault dictionary: New approaches and implementation.” Circuit Theory and Applications 12, pp. 149–172, John Wiley & Sons, 1985.CrossRefGoogle Scholar
  2. 2.
    M. J. Marlett and J. A. Abraham, “DC-IATP: An iterative analog circuit test generation program for generating DC single pattern tests,” in Proc. IEEE International Test Conference, pp. 839–845, 1988.Google Scholar
  3. 3.
    L. Rapisarda and R. DeCarlo, “Analog multifrequency fault diagnosis.” IEEE Trans. Circuits Syst. CAS-30, pp. 223–234, April 1983.CrossRefGoogle Scholar
  4. 4.
    T. M. Souders and G. N. Stenbakken, “A comprehensive approach for modeling and testing analog and mixed-signal devices,” in Proc IEEE International Test Conference, pp. 169–176, 1990.Google Scholar
  5. 5.
    L. Milor and A. Sangiovanni-Vincentelli, “Optimal test set design for analog circuits,” in Proc. IEEE ICCAD 1990.Google Scholar
  6. 6.
    A. Meixner and W. Maly, “Fault modeling for the testing of mixed integrated circuits,” Research report No. CMUCAD-91–6, Feb. 1991.Google Scholar
  7. 7.
    M. Soma, “A Design-for-Test Methodology for Active Analog Filters,” in Proc. IEEE International Test Conference pp. 183–192, 1990.Google Scholar
  8. 8.
    C-Y. Pan, K-T. Cheng, and S. Gupta, “A comprehensive fault macromodel for opamps,” in Proc. ICCAD, pp. 344–348,1994Google Scholar
  9. 9.
    H. Hao and E. J. McCluskey. “‘Resistive shorts’ within CMOS gates,” in Proc. IEEE International Test Conference, 1991, pp. 292–301.Google Scholar
  10. 10.
    R. Harvey, A. Richardson, E. Bruls, and K. Baker, “Analog fault simulation based on layout dependent fault models,” in Proc. IEEE International Test Conference, pp. 641–649,1994.Google Scholar
  11. 11.
    J. Shao and R. Harjani, “Macromodeling of analog circuits for hierarchical circuit design,” in Proc. ICCAD, pp. 656–663, 1994.Google Scholar
  12. 12.
    N. Nagi and J. A. Abraham, “Hierarchical fault modeling for analog and mixed-signal circuits,” in Proc. IEEE VLSI Test Symposium, pp. 96–101, 1992.Google Scholar
  13. 13.
    J. P. Shen, W. Maly, and F. J. Ferguson, “Inductive fault analysis of MOS integrated circuits.” IEEE Design and Test 2, pp. 13–26, Dec. 1985.CrossRefGoogle Scholar
  14. 14.
    D. M. H. Walker and S. W Director, “VLASIC: A catastrophic fault yield simulator for integrated circuits.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 541–556, Oct. 1986.Google Scholar
  15. 15.
    S. R. Nassif, A. J. Strojwas, and S. W Director, “FABRICS II: A statistically based IC fabrication process simulator.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 40–46, Jan. 1994.Google Scholar
  16. 16.
    B. R. Epstein, M. Czigler, and R. Miller, “Fault detection and classification in linear integrated circuits: An application of discrimination analysis and hypothesis testing.” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, pp. 102–113, Jan. 1993.Google Scholar
  17. 17.
    T. Yu, S. Kang, I. Hajj, and T. Trick, “Statistical performance modeling and parametric yield estimation of MOS VLSI circuits.” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Nov. 1987.Google Scholar
  18. 18.
    L. T. Pillage and R. A. Rohrer, “Asymptotic waveform evaluation for timing analysis.” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Apr. 1990.Google Scholar
  19. 19.
    P. A. Allen and E. Sanchez-Sinencio, Switched Capacitor Circuits. Van Nostrand Reinhold Company, 1984.Google Scholar
  20. 20.
    M. Renovell and G. Cambon, “Topology dependence of floating gate faults in MOS integrated circuits.” Electronic Letters 22(3), pp. 152–153.Google Scholar
  21. 21.
    C. L. Ratzlaff, N. Gopal and L. T. Pillage, “RICE: Rapid Interconnect Circuit Evaluator,” in Proc. ACM/IEEE Design Automation Conference, 1991.Google Scholar
  22. 22.
    N. Nagi, A. Chatterjee, and J. A. Abraham, “Fault simulation of linear analog circuits.” Journal of Electronic Testing: Theory and Applications 4, pp. 345–360, 1993.CrossRefGoogle Scholar

Copyright information

© Kluwer Academic Publishers, Boston 1996

Authors and Affiliations

  • Naveena Nagi
    • 1
  • Jacob A. Abraham
    • 2
  1. 1.LogicVisionSan JoseUSA
  2. 2.Computer Engineering Research CenterUniversity of Texas at AustinAustinUSA

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