Abstract
We considered the physical design and optimization formulation for simultaneous power I/O cell assignment, power bus topology, and power bus sizing synthesis in the proceeding chapter, but we have still only addressed part of the problem. In this chapter, we complete our power distribution synthesis formulation by describing the electrical modeling and electrical evaluation strategy used to meet our electrical objectives and constrain DC, AC, and transient behavior. We highlight AC and transient behavior, the major concerns as yet unaddressed to our knowledge in power synthesis. We will describe a method to consider this critical part of design in mixed-signal integrated circuits and also describe improvements in handling DC behavior.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
J. Hall, D. Hocevar, et al., “SPIDER-A CAD System for Modeling VLSI Metallization Patterns”, IEEE Transactions on Computer-Aided Design, Vol. 6, No. 6, pp. 1023–1031, November 1987.
S. Chowdhury and M. A. Breuer, “Minimal Area Sizing of Power and Ground Nets for VLSI Circuits”, In Proceedings 4th MIT Conference on Advanced Research in VLSI, pp. 141–169, April, 1986.
R. Kolla, “A Dynamic Programming Approach to the Power Supply Net Sizing Problem”, In Proceedings European Design Automation Conference, pp. 600–604, March 1990.
H. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, in Chapter 7, “Crosstalk and Power Distribution Noise”, pp. 281–337, Addison-Wesley Publishing Co., Reading MA, 1990.
G. A. Katopis, “Delta-I Noise Specification for a High-Performance Computing Machine”, In Proceedings of the IEEE, Vol. 73, No. 9, pp. 1405–1415, September 1985.
R. Senthinathan, J. L. Prince, “Simultaneous Switching Ground Noise Calculation for Packaged CMOS Devices”, IEEE Journal of Solid-State Circuits, Vol. 26, No. 11, pp. 1724–1728, November 1991.
F. N. Najm, “Power Estimation Techniques for Integrated Circuits”, In Proceedings IEEE International Conference on Computer-Aided Design, pp. 492–499, November 1995.
R. Burch, F. Najm, P. Yang, and D. Hocevar, “Pattern-Independent Current Estimation for Reliability Analysis of CMOS Circuits”, In Proceedings 25th Design Automation Conference, pp. 294–299, June 1988.
S. Chowdhury and J. Barkatullah, “Current Estimation in MOS IC Logic Circuits”, In Proceedings IEEE International Conference on Computer-Aided Design, pp. 212–215, November 1988.
A. Deng, Y. Shiau, and K. Loh, “Time Domain Current Waveform Simulation of CMOS Circuits”, In Proceedings IEEE International Conference on Computer-Aided Design, pp. 208–211, November 1988.
F. Najm, R. Burch, P. Yang, and I. Hajj, “CREST — A Current Estimator for CMOS Circuits”, In Proceedings IEEE International Conference on Computer-Aided Design, pp. 204–207, November 1988.
T. Wada, M. Eino, K. Anami, “Simple Noise Model and Low-Noise Data-Output Buffer for Ultrahigh-Speed Memories”, IEEE Journal of Solid-State Circuits, Vol. 25, No. 6, pp. 1586–1588, December 1990.
F. N. Najm and M. Y. Zhang, “Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuits”, In Proceedings 32nd Design Automation Conference, pp. 623–627, June 1995.
G. Frenkil, “Power Dissipation of CMOS ASICs”, In Proceedings IEEE ASIC Conference, pp. T3–1.1 to T3–1.5, September 1991.
J. A. Olmstead, S. Vulih, “Noise Problems in Mixed Analog-Digital Integrated Circuits”, In Proceedings IEEE Custom Integrated Circuits Conference, pp. 659–662, April 1987.
T. Schmerbeck, R. Richetta, and L. Smith, “A 27MHz Mixed Analog/Digital Magnetic Recording Channel DSP Using Partial Response Signalling with Maximum Likelihood Detection”, In Proceedings IEEE International Solid-State Circuits Conference, pp. 136–137 & 304, February 1991.
N. Verghese, T. Schmerbeck, and D. Allstot, Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits, in Chapter 8, “Modeling Chip/Package Power Distribution”, pp. 149–182, Kluwer Academic Publishers, Boston MA, 1995.
N. Verghese, T. Schmerbeck, and D. Allstot, Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits, in Chapter 9, “Controlling Substrate Coupling in Heavily-Doped Bulk Processes”, pp. 183–216, Kluwer Academic Publishers, Boston MA, 1995.
D. K. Su, M. Loinaz, S. Masui, and B. Wooley, “Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits”, IEEE Journal of Solid-State Circuits, Vol. 28, No. 4, pp. 420–430, April 1993.
N. Verghese, D. Allstot, and S. Masui, “Rapid Simulation of Substrate Coupling Effects in Mixed-mode IC’s”, In Proceedings IEEE Custom Integrated Circuits Conference, pp. 18.3.1–18.3.4, May 1993.
N. Verghese, T. Schmerbeck, and D. Allstot, Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits, in Chapter 6, “Substrate Modeling in Heavily-Doped Bulk Processes”, pp. 125–129, Kluwer Academic Publishers, Boston MA, 1995.
L. Ladage, R. Leupers, “Resistive Extraction Along the Current Flow”, in Proceedings IEEE Custom Integrated Circuits Conference, pp. 17.5.1–17.5.4, May 1993.
R. Antinone and G. Brown, “The Modeling of Resistive Interconnects for Integrated Circuits”, IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 2, pp. 200–203, April 1983.
T. Sakurai, K. Tamaru, “Simple Formulas for Two-and Three-Dimensional Capacitances”, IEEE Transactions on Electron Devices, Vol. ED-30, No. 2, pp. 183–185, February 1983.
C. P. Yuan, T. N. Trick, “A simple Formula for the Estimation of the Capacitance of Two-Dimensional Interconnects in VLSI Circuits”, IEEE Electron Device Letters, EDL-3, No. 12, pp. 391–393, December 1982.
T. Gabara, “Reduced Ground Bounce and Improved Latch-Up Suppression Through Substrate Conduction”, IEEE Journal of Solid-State Circuits, Vol. 23, No. 5, pp. 1224–1232, October 1988.
A. J. Rainal, “Computing Inductive Noise of Chip Packages”, AT&T Bell Laboratories Technical Journal, Vol. 63, No. 1, pp. 177–195, January 1984.
T. Schmerbeck, “Mechanisms and Effects of Noise Coupling in Analog ICs”, in presentation for course on Practical Aspects of Analog and Mixed-Mode IC Design, Beaverton Oregon, May 18, 1993.
H. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, in Chapter 6, “Transmission Lines”, pp. 226–280, Addison-Wesley Publishing Co., Reading MA, 1990.
N. Verghese, T. Schmerbeck, and D. Allstot, Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits, in Chapter 2, “Sources of Noise and Methods of Coupling”, pp. 5–42, Kluwer Academic Publishers, Boston MA, 1995.
S. Kumasiro, R. Rohrer, and A. Strojwas, “A new efficient method for the transient simulation of three-dimensional interconnect structures”, in Proceeding of the IEEE International Electron Devices Meeting, pp. 193–196, 1990.
B. Stanisic, N. Verghese, R. Rutenbar, L. R. Carley, and D. Allstot, “Addressing Substrate Coupling in Mixed-Mode IC’s: Simulation and Power Distribution Synthesis”, IEEE Journal of Solid-State Circuits, Vol. 29, No. 3, pp. 226–238, March 1994.
T. Schmerbeck, “Design Strategies for Reducing the Effects of Noise Coupling in Analog and Mixed-Mode ICs”, in presentation for course on Practical Aspects of Analog and Mixed-Mode IC Design, Beaverton Oregon, May 18, 1993.
R. van de Grift, “Design Methodology for mixed signal ICs, Philips Electronic Design & Tools, the Netherlands”, presented at Carnegie-Mellon University, February 27, 1992.
L. Nagel and R. Rohrer, “Computer Analysis of Nonlinear Circuits Excluding Radiation (CANCER)”, IEEE Journal of Solid-State Circuits, vol. SC-6, No. 4, pp. 166–182., August 1971.
C. Ho, A. Ruehli, and P. Brennan, “The Modified Notai Approach to Network Analysis”, IEEE Transactions on Circuits and Systems, Vol. CAS-22, No. 6, pp. 504–509, June 1975.
S. Chowdhury, “An Automated Design of Minimum-Area IC Power/Ground Nets”, In Proceedings 24th Design Automation Conference, pp. 223–229, June 1987.
G. Gielen, et al., “Analog circuit design optimization based on symbolic simulation and simulated annealing”, IEEE Journal of Solid-State Circuits, vol. SC-25, no. 3, pp. 707–713, June 1990.
W. Nye, D. Riley, and A. Sangiovanni-Vincentelli, “Delight.SPICE: An Optimization-Based System for the Design of Integrated Circuits”, IEEE Transactions on Computer-Aided Design, Vol. CAD-7, No. 4, pp. 501–518, April 1988.
L. Pillage and R. Rohrer, “Asymptotic Waveform Evaluation for Timing Analysis”, IEEE Transactions on CAD, Vol. 9, No. 4, pp. 352–366, April 1990.
E. Ochotta, R. Rutenbar, and L. Carley, “Equation-Free Synthesis of High-Performance Linear Analog Circuits”, Brown/MIT Conference on VLSI and Parallel Systems, pp. 129–143, April 1992.
M. Alaybeyi, J. Y. Lee, and R. Rohrer, “Numerical Integration and Asymptotic Waveform Evaluation”, In Proceedings IEEE International Conference on Computer-Aided Design, pp. 76–79, November 1992.
V. Raghavan, R. Rohrer, et al. “AWE Inspired”, In Proceedings IEEE Custom Integrated Circuits Conference, pp. 18.1.1–18.1.8, May 1993.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 1996 Kluwer Academic Publishers
About this chapter
Cite this chapter
Stanisic, B.R., Rutenbar, R.A., Carley, L.R. (1996). DC, AC, and Transient Electrical Models and Analysis. In: Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1399-1_4
Download citation
DOI: https://doi.org/10.1007/978-1-4613-1399-1_4
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4612-8606-6
Online ISBN: 978-1-4613-1399-1
eBook Packages: Springer Book Archive