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From Contamination to Defects, Faults and Yield Loss

Part of the book series: Frontiers in Electronic Testing ((FRET,volume 5))

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Abstract

In this chapter, we briefly discuss previous attempts at modeling contamination in IC manufacturing and its effect on yield modeling. The relevance of these models in modern manufacturing environments is also discussed.

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Authors and Affiliations

  1. Carnegie Mellon University, USA

    Jitendra B. Khare & Wojciech Maly

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  1. Jitendra B. Khare
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  2. Wojciech Maly
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© 1996 Kluwer Academic Publishers

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Khare, J.B., Maly, W. (1996). Background. In: From Contamination to Defects, Faults and Yield Loss. Frontiers in Electronic Testing, vol 5. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1377-9_2

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  • DOI: https://doi.org/10.1007/978-1-4613-1377-9_2

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4612-8595-3

  • Online ISBN: 978-1-4613-1377-9

  • eBook Packages: Springer Book Archive

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