Abstract
Over the years, there has been a large increase in functionality available on a single integrated circuit. From 2,300 transistors on a chip in 1971 [1], the state-of-the art designs of today have progressed to about 5 million transistors [2], [3]. The number of transistors on a single die has approximately doubled every two years, as predicted by Moore’s law [4].
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI, Addison-Wesley Publishing Co., Reading, MA, 1990.
R. P. Colwell and R. L. Steck, “A 0.6µm BiCMOS Processor with Dynamic Execution,” Proceedings of the 1995 International Solid State Circuits Conference, pp. 176–177, 1995.
T. R. Halfill, “Intel’s P6,” Byte, vol. 20, no. 5, pp. 42–58, April 1995.
G. Moore, “VLSI: Some Fundamental Challenges,” IEEE Spectrum, vol. 16, p. 30, 1979.
W. Maly, “Prospects for WSI: A Manufacturing Perspective,” IEEE Computer Magazine, vol. 25 no. 4, pp. 58–65, April 1992.
W. Maly, “Cost of Silicon Viewed from VLSI Design Perspective,” Proceedings of the 1994 Design Automation Conference, pp. 135–142, 1994.
S. Director and W. Maly and A. J. Strojwas, VLSI Design for Manufacturing Yield Enhancement, Kluwer Academic Publishers, Boston, 1990.
W. Maly, “Computer-Aided Design for VLSI Circuit Manufacturability,” Proceedings of the IEEE, vol. 78 no. 2, pp. 356–392, February 1990.
W. Maly and A. J. Strojwas and S. W. Director, “VLSI Yield Prediction and Estimation: A Unified Framework,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-5, no. 1, pp. 114–130, January, 1986.
W. Maly and A. J. Strojwas, “Statistical Simulation of the IC Manufacturing Process,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 1 no. 3, pp. 12–131, July 1982.
W. Maly, “Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 4 no. 4, pp. 166–177, July 1985.
B. T. Murphy, “Cost-Size Optima of Monolithic Integrated Circuits,” Proceedings of the IEEE, vol. 52, no. 12, pp. 1537–1545, December 1964.
T. Lawson, “A Prediction of the Photoresist Influence on Integrated Circuit Yield,” IEEE Journal of Solid State Technology, vol. 9, no. 7, pp. 22–25, July 1966.
R. B. Seeds, “Yield, Economic, and Logistic Models for Complex Digital Arrays,” IEEE International Convention Record, pp. 6–61. March 1967.
A. Gupta and J. Lathrop, “Comments on Influence of Epitaxial Mounds on the Yield of Integrated Circuits,” Proceedings of the IEEE, vol. 58, no. 12, pp. 196–1961, December 1970.
R. M. Warner Jr., “Applying a Composite Model to the IC Yield Problem,” IEEE Journal of Solid State Circuits, vol. SC-9, no. 3, pp. 86–95, June 1974.
T. Okabe, M. Nagata and S. Shimada, “Analysis of Yield of Integrated Circuits and a New Expression for Yield,” Electrical Engineering in Japan, vol. 92, pp. 135–141, December 1972.
E. Muehldorf, “Fault Clustering: Modeling and Observation on Experimental LSI Chips,” IEEE Journal of Solid-State Circuits, vol. SC-10, no. 4, pp. 237–244, August 1975.
C. H. Stapper, A. McLaren and M. Dreckmann, “On a Composite Model to the IC Yield Problem,” IEEE Journal of Solid State Circuits, vol. SC-10, no. 6, pp. 537–539, December 1975.
C. H. Stapper, “LSI Yield Modeling and Process Monitoring,” IBM Journal of Research and Development, vol. 20, no. 3, pp. 228–234, May 1976.
C. H. Stapper, A. McLaren and M. Dreckmann, “Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product,” IBM Journal of Research and Development, vol. 24, no. 3, pp. 398–409, May 1980.
C. H. Stapper, “Comments on Some Considerations in the Formulation of IC Yield Statistics,” Solid-State Electronics, vol. 24, no. 2, pp. 127–132, February 1981.
C. H. Stapper and R. Rosner, “A Simple Method for Modeling VLSI Yields,” Solid-State Electronics, vol. 25, no. 6, pp. 487–489, June 1982.
W. Maly and J. Deszczka, “Yield Estimation Model for VLSI Artwork Evaluation,” Electronics Letters, vol. 19 no. 6, pp. 226–227, March 1983.
M. Ketchen, “Point Defect Yield Model for Wafer Scale Integration,” IEEE Circuits and Devices Magazine, vol. 1 no. 4, pp. 24–34, July 1985.
D. M. H. Walker and S. W. Director, “VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 5 no. 4, pp. 541–556, October 1986.
F. J. Ferguson, Inductive Fault Analysis of VLSI Circuits, Ph.D. Thesis, Carnegie Mellon University, Pittsburgh, PA, 1987.
Jose Pineda de Gyvez, IC Defect-Sensitivity: Theory and Computational Models for Yield Prediction, Ph.D. Thesis, Technische Universiteit Eindhoven, April 1991.
J. Khare, A New Methodology for Yield Simulation of Integrated Circuits, Masters Thesis, Department of Electrical Engineering, Carnegie Mellon University, May 1989.
D. Feltham, J. Khare and W. Maly, “A CAD Tool for Accurate Yield Estimation for Reconfigurable VLSI Circuits,” SRC-CMU Research Center for Computer-Aided Design — Report CMUCAD-92–28, Carnegie Mellon University, Pittsburgh, PA, April 1992.
P. K. Nag and W. Maly, “Fast Critical Area Extraction for Shorts in VLSI ICs,” SRC-CMU Center for Computer-Aided Design Research Report, Carnegie Mellon University, 1993.
I. Wagner and I. Koren, “An Interactive Yield Estimator as a VLSI CAD Tool,” Proceedings of the IEEE International Workshop on Defect and Fault Tolerance on VLSI Systems, pp. 167–174, 1993.
H. Xue, C. Di and J. A. G. Jess, “Fast Multi-Layer Critical Area Computation,” Proceedings of the IEEE International Workshop on Defect and Fault Tolerance on VLSI Systems, pp. 117–124, 1993.
D. Gaitonde, Design and Application of a Hierarchical Defect to Fault Mapper, Ph. D. Thesis, Carnegie Mellon University, February 1995.
I. Bubel, W. Maly, T. Waas, P. K. Nag, H. Hartman, D. Schmitt-Landsiedel and S. Griep, “AFFCCA: A Tool for Critical Area Analysis with Circular Defects and Lithography Deformed Layout,” Proceedings of the IEEE Workshop on Defect and Fault Tolerance on VLSI Systems, November 1995.
T. L. Michalka, R. C. Varshney and J. D. Meindl, “A Discussion of Yield Modeling with Defect Clustering, Circuit Repair, and Circuit Redundancy,” IEEE Transactions on Semiconductor Manufacturing, vol. 3, no. 3, pp. 116–127, August 1990.
R. Y. Rubinstein, Simulation and The Monte Carlo Method, John Wiley & Sons, 1981.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 1996 Kluwer Academic Publishers
About this chapter
Cite this chapter
Khare, J.B., Maly, W. (1996). Introduction. In: From Contamination to Defects, Faults and Yield Loss. Frontiers in Electronic Testing, vol 5. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1377-9_1
Download citation
DOI: https://doi.org/10.1007/978-1-4613-1377-9_1
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4612-8595-3
Online ISBN: 978-1-4613-1377-9
eBook Packages: Springer Book Archive