Pipelining of Lattice IIR Digital Filters

  • Jin-Gyun Chung
  • Keshab K. Parhi
Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 344)


In this chapter, we address pipelining of lattice digital filters. Although the lattice filters can be pipelined by the cutset localization procedure, the maximum sample rate of these pipelined filters is limited by the feedback loop computations. For example, in normalized lattice filters, the cutset localization procedure can be applied to transfer one half of each delay on the right directed edges to the left directed edges as shown in Fig. 7.1. The half delays can be implemented by time rescaling. For example, using one clock cycle to represent a half delay, we can input one sample every two clock cycles and generate the output samples once every two clock cycles. With this transformation, the clock speed can be increased, but the sample rate cannot be increased, since multiple clock cycles are needed to process one sample. The maximum sample rate of this structure is limited by the feedback loop computation which involves two multiplications and two additions.

Fig. 7.1

Third order normalized lattice filter with transferred half delays.


Clock Cycle Digital Filter Nonzero Coefficient Consecutive Zero Zero Coefficient 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Kluwer Academic Publishers 1996

Authors and Affiliations

  • Jin-Gyun Chung
    • 1
  • Keshab K. Parhi
    • 2
  1. 1.Chonbuk National UniversityKorea
  2. 2.University of MinnesotaUSA

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