Architectural Trade-Offs for Implementing Video Encoders

Abstract

Designing VLSI chips to implement video encoders capable of realtime MPEG-2 compression at MP@ML or MP@HL levels of resolution is an extremely challenging task. The computational requirements are enormous and, to date, there are no single chip solutions that support the full richness of functionality available in MPEG-2’s Main Profile. As silicon technology continues to evolve, there is no doubt that function-rich, single-chip, MPEG-2 encoders will exist in the future. However, with today’s technology we must be content with multiple-chip solutions or, alternatively, with less than full Main Profile functionality in a single chip. If a full-function MP@ML implementation is the goal, a VLSI designer needs to make a number of architectural decisions that impact the flexibility and complexity of the chip or chips, as well as the cost of a system that incorporates them. We distinguish between two approaches to this problem.