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Steiner Tree Problems in VLSI Layout Designs

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Book cover Steiner Trees in Industry

Part of the book series: Combinatorial Optimization ((COOP,volume 11))

Abstract

Given a signal net N = s,1, … , n to be the set of nodes, with s the source and the remaining nodes sinks, an MRDPT (minimum-cost rectilinear Steiner distance-preserving tree) has the property that the length of every source to sink path is equal to the rectilinear distance between the source and sink. The minimum-cost rectilinear Steiner distance-preserving tree minimizes the total wire length while maintaining minimal source to sink length. Recently, some heuristic algorithms have been proposed for the problem of finding the MRDPT. In this paper, we investigate a condition that leads to an optimal structure on the MRDPT. A more practical application to VLSI clock designs is also investigated along with interesting open problems.

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References

  1. R. K. Ahuja, T. L. Magnanti, and J. B. Orlin. “Network Flows”. Prentice Hall, Englewood Cliffs, New Jersey 07632, 1993.

    Google Scholar 

  2. P. Barth. “Generalized Integer Program:an implementation of an im-plicit enumeration algorithm solving linear 0–1 optimization problems”. http://www.ftp.mpi-sb.mpg.de:/pub/guide/staff/barth/opbdp.com, 1997.

    Google Scholar 

  3. P. Berman. “http://www.berman@cse.psu.edu.com”. private communication, May 1997.

    Google Scholar 

  4. H. A. Choi and A. H. Esfahanian. On complexity of a message-routing strategy for multicomputer systems. In the 16th International Workshop on Graph-Theoretic Concepts in Computer Science, Germany, pages 170–181, 1990.

    Google Scholar 

  5. J.D.Cho. “A Min-Cost Flow Based Min-Cost Rectilinear Steiner Distance-Preserving Tree Construction”. In In proceedings of 1997 IEEE/ACM International Symposium on Physical Design, pages 82–87, 1997.

    Chapter  Google Scholar 

  6. C. H. Papadimitriou and K. Steiglitz. Combinatorial Optimization, chapter “Weighted Matching”, pages 247–270. Prentice-Hall, Inc., Englewood Cliffs, NJ 07632, 1982.

    MATH  Google Scholar 

  7. J. Cong, A. Kahng, C. K. Koh, and C. W. Tsao. “Bounded-Skew Clock and Steiner Routing Under Elmore Delay”. In International Conference on Computer-Aided Design, page Issues in Clock Designs, 1995.

    Google Scholar 

  8. J. Cong, A. Kahng, and K-S Leung. “Efficient Heuristics for the Minimum Shortest Path Steiner Arborescence Problem with Applications to VLSI Physical Design”. In In proceedings of 1997 IEEE/ACM International Symposium on Physical Design, pages 88–95, 1997.

    Chapter  Google Scholar 

  9. J. Cong, K.-S. Leung, and D. Zhou, “Performance-Driven Interconnect Design Based on Distributed RC Delay Model”. In UCLA Computer Science Department Technical Report CSD-920043,Oct. 1992.

    Google Scholar 

  10. J. D. Cho and M. Sarrafzadeh. “Buffer Distribution Algorithm for High-Performance Clock Optimization”. IEEE Transactions on VLSI Systems, 3(4):84–98, 1995.

    Google Scholar 

  11. A.I. Erzin, S.H. Kim, and J.D. Cho. “”Deep-Submicron Rectilinear Steiner Tree Problem”. In Proceedings of the 5-th Int. Conf. On VLSI and CAD, Seoul, pages 241–243, 1997.

    Google Scholar 

  12. A. I. Erzin and S.H. Kim. “ “Polynomial Approximation Algorithm for Min-Cost Delays-Constrained Multicasting Routing Problem in Networks”. In Proceedings of the 1-st Int. Conf. on Information,Communications and Signal Processing,Singapore, pages 1805–1809, 1997.

    Google Scholar 

  13. E. G. Friedman. “Clock Distribution. Networks in VLSI Circuits and Systems”. IEEE, 1995.

    Google Scholar 

  14. M. R. Garey and D. S. Johnson. “The Rectilinear Steiner Tree Problem is NP-Complete”. SIAM Journal on Applied Mathematics, 32(4):826–834, April 1977.

    Article  MathSciNet  MATH  Google Scholar 

  15. M. R. Garey and D. S. Johnson. Computers and Intractability: A Guide to the Theory of NP-completeness. Freeman, 1979.

    MATH  Google Scholar 

  16. M. Hanan. “On Steiner’s Problem with Rectilinear Distance”. SIAM Journal on Applied Mathematics, 14(2):255–265, February 1966.

    Article  MathSciNet  MATH  Google Scholar 

  17. X. Hong, T. Xue, E. S. Kuh, C. K. Cheng, and J. Huang. “Performance-Driven Steiner Tree Algorithms for Global Routings”. In Design Automation Conference, 1993.

    Google Scholar 

  18. Kennington and Helgason. “ “Algorithms for Network Programming,” In John Wiley„ pages 244–256 (NETFLOW program), 1980.

    Google Scholar 

  19. A. B. Kahng and G. Robins. “On Optimal Interconnections for VLSI”. Kluwer Academic Publishers, Norwell, MA, 1995.

    Google Scholar 

  20. A. Lim and S. W. Cheng. “Performance-Oriented Rectilinear Steiner Trees”. In Design Automation Conference, pages 171–176, 1992.

    Google Scholar 

  21. H. Mitsubayashi, A. Takahashi, and Y. Kajitani. “Cost-Radius Balanced Spanning/Steiner Trees”. Proceedings of IEEE Asia Pacific Conference on Circuits and Systems, pages 377–380, Jan 1996. in IEICE Trans. Fundamentals, V. E80-A, No. 4, April 1997.

    Google Scholar 

  22. I. Pyo, J. Oh, and M. Pedram. “Constructing Minimal Span- ning/Steiner Trees with Bounded Path Length”. In European Design and Test Conference, pages 244–248, 1996.

    Chapter  Google Scholar 

  23. C. H. Papadimitriou and K. Steiglitz. Combinatorial Optimization - Algorithms and Complexity. Prentice-Hall, 1982.

    MATH  Google Scholar 

  24. S. K. Rao, P. Sadayappan, F. K. Hwang, and P. W. Shor. “The rectilinear Steiner arborescence problem”. Algorithmica, vol.7, (no.2–3):277–88, 1992.

    Article  MathSciNet  MATH  Google Scholar 

  25. J.S.Salowe. “Thirty-Five-Point Rectilinear Steiner Trees in a Day”. Networks, 25, 1995.

    Google Scholar 

  26. Minshine Shih and Ernest S. Kuh. “Circuit Partitioning under Capacity and I/O Constraints”. In IEEE Custom Integrated Circuits Conference. IEEE, 1994.

    Google Scholar 

  27. M. Sriram and S. M. Kang. “Physical Design for Multichip Modules”. Kluwer Academic Publishers, 1994.

    Google Scholar 

  28. G. Tellez and M. Sarrafzadeh. “On Rectilinear Distance-Preserving Trees”. Manuscript, To appear in VLSI DESIGN, the special issue in high performance Design Automation for VLSI interconnections, May 1995.

    Google Scholar 

  29. A. Vittal and M. Marek-Sadowska. “Minimal Delay Interconnect Design using Alphabetic Trees”. In Design Automation Conference, pages 392–396, 1994.

    Google Scholar 

  30. P. Winter. Steiner Problem in Networks: A Survey”. Networks, 17:129–167, 1987.

    Article  MathSciNet  MATH  Google Scholar 

  31. J. G. Xi and W. W.-M Dai. “Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution”. In Design Automation Conference, pages 491–496, 1995.

    Google Scholar 

  32. M. Afghahi and C. Svensson. “Performance of Synchronous and Asynchronous Schemes for VLSI Systems”. IEEE Transactions on Computers, 41(7):858–872, 1992.

    Article  Google Scholar 

  33. D. Avis. “Worst Case Bounds for the Euclidean Matching Problem”. International J. Comput. Math. Appl., 7:251–257, 1981.

    Article  MathSciNet  MATH  Google Scholar 

  34. H. B. Bakoglu. “Circuits, Interconnections, and Packaging for VLSI”, pages 81–112. Addison-Wesley Publishing Co., 1990.

    Google Scholar 

  35. K. D. Boese and A. B. Kahng. “Zero-Skew Clock Routing With Minimum Wirelength”. In Proceedings of the Fifth Annual IEEE International ASIC Conference and Exhibit, pages 17–21. IEEE, September 1992.

    Chapter  Google Scholar 

  36. H. Bakoglu, J. T. Walker, and J. D. Meindl. “A Symmetric Clock-Distribution Tree and Optimized High-Speed Interconnections for Reduced Clock Skew in ULSI and WSI Circuits”. In International Conference on Computer Design, pages 118–122. IEEE, October 1986.

    Google Scholar 

  37. T. H. Chao, Y. C. Hsu, and J. M. Ho. “Zero Skew Clock Net Routing”. In Design Automation Conference, pages 518–523. IEEE/ACM, 1992.

    Google Scholar 

  38. T. H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese, and A. B. Kahng. “Zero Skew Clock Routing with Minimum Wirelength”. IEEE Transactions on Circuits and Systems, 39(11):799–814, 1992.

    Article  MATH  Google Scholar 

  39. N. Christofides. “Worst Case Analysis of a New Heuristic for the Traveling Salesman Problem”. Technical report, Management Science Research Rept. 388, Carnegie-Mellon University, Pittsburgh, PA, 1976.

    Google Scholar 

  40. J. Cong, A. Kahng, G. Robins, M. Sarrafzadeli. and C. K. Wong. “Provably Good Performance-Driven Global Routing”. IEEE Transactions on Computer Aided Design, 11(6):739–752, June 1992.

    Article  Google Scholar 

  41. A. E. Dunlop, V. D. Agrawal, D. N. Deutsch, M. F. Jukl, P. Kozak, and M. Wiesel. “Chip Layout Optimization Using Critical Path Weighting” In Design Automation Conference, pages 133–136. IEEE/ACM, 1984.

    Google Scholar 

  42. M. Edahiro. “A Clustering-Based Optimization Algorthm in Zero-Skew Routings”. In Design Automation Conference, pages 612–616. IEEE/ACM, 1993.

    Google Scholar 

  43. W. C. Elmore. “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers”. J. Applied Phys., 19(1):55–63, Jan. 1948.

    Article  Google Scholar 

  44. M. Fürer and B. Raghavachari. “Approximating the Minimum Degree Spanning Tree to within one from the Optimal Degree”. In Ann. ACM-SIAM Symp. on Discrete Algorithm, volume 4, pages 317–324, 1992.

    Google Scholar 

  45. P. D. Franzen. Private communication. Electronic MCM Clearing House in North Carolina State University, 1992.

    Google Scholar 

  46. F. K. Hwang. “An O(nlogn) Algorithm for Suboptimal Rectilinear Steiner Trees”. IEEE Transactions on Circuits and Systems, CAS-26(1):75–77, January 1979.

    Article  Google Scholar 

  47. M. A. B. Jackson, E. S. Kuh, and M. Marek-Sadowska. “Timing-Driven Routing for Building Block Layout”. In International Symposium, on Circuits and Systems, pages 518–519. IEEE, 1987.

    Google Scholar 

  48. M. A. B. Jackson, A. Srinivasan, and E. S. Kuh. “Clock Routing for High-Performance ICs”. In Design Automation Conference, pages 573–579. IEEE/ACM, 1990.

    Google Scholar 

  49. A. Kahng, J. Cong, and G. Robins. “High-Performance Clock Routing Based on Recursive Geometric matching”. In Design Automation Conference, pages 322–327. IEEE/ACM, 1991.

    Google Scholar 

  50. S. Prasitjutrakul and W. J. Kubitz. “A Timing-Driven Global Router for Custom Chip Design”. In International Conference on Computer-Aided Design, pages 48–51. IEEE, November 1990.

    Google Scholar 

  51. S. Pullela, N. Menezes, and L. T. Pillage. “Reliable Non-Zero Skew Clock Tree Using Wire Width Optimization”. In Design Automation Conference, pages 165–170. ACM/IEEE, June 1993.

    Google Scholar 

  52. C. H. Papadimitriou and K. Steiglitz. Combinatorial Optimization, chapter “Weighted Matching”, pages 247–270. Prentice-Hall, Inc., Englewood Cliffs, NJ 07632, 1982.

    MATH  Google Scholar 

  53. F. P. Preparata and M. I. Shamos. Computational Geometry: An Introduction. Springer-Verlag, 1985.

    Google Scholar 

  54. T. Sakurai. “Approximation of Wiring Delay in MOSFET LSI”. IEEE Journal of Solid-State Circuits, 18(4):418–426, 1983.

    Article  Google Scholar 

  55. T. L. Snyder. “Lower Bounds for Rectilinear Steiner Trees in Bounded Space”. Information Processing Letters, 37:71–74, 1991.

    Article  MathSciNet  MATH  Google Scholar 

  56. K. J. Supowit, E. M. Reingold, and D. A. Plaisted. “The Travelling Salesman Problem and Minimum Matching in the Unit Square”. SIAM J. Computing, 12:144–156, 1983.

    Article  MathSciNet  MATH  Google Scholar 

  57. J. M. Steele. “Probabilistic and Worst Case Analyses of Classical Problems of Combinatorial Optimization in Euclidean Space”. Mathematics of Operations Research, 15(5):749–771, 1990.

    Article  MathSciNet  MATH  Google Scholar 

  58. R-S. Tsay. “Exact Zero Skew”, In International Conference on Computer-Aided Design, pages 336–339. IEEE/ACM, 1991.

    Google Scholar 

  59. P. Vaidya. “Geometry Helps in Matching”. In ACM Symp on the Theory of Computing, pages 422–425, 1988.

    Google Scholar 

  60. L.P.P.P. van Ginneken. “Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay”. In International Symposium on Circuits and Systems, pages 865–868, 1990.

    Chapter  Google Scholar 

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Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Korea

    Jun-Dong Cho

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  1. Jun-Dong Cho
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Editor information

Editors and Affiliations

  1. Department of Computer Science and Engineering, University of Minnesota, Minneapolis, MN, USA

    Xiu Zhen Cheng  & Ding-Zhu Du  & 

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© 2001 Kluwer Academic Publishers

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Cho, JD. (2001). Steiner Tree Problems in VLSI Layout Designs. In: Cheng, X.Z., Du, DZ. (eds) Steiner Trees in Industry. Combinatorial Optimization, vol 11. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-0255-1_4

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  • DOI: https://doi.org/10.1007/978-1-4613-0255-1_4

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-7963-8

  • Online ISBN: 978-1-4613-0255-1

  • eBook Packages: Springer Book Archive

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