The Limitations to Delay-Insensitivity in Asynchronous Circuits
Asynchronous techniques —that is, techniques that do not use clocks to implement sequencing— are currently attracting considerable interest for digital VLSI circuit design, in particular when the circuits produced are delay-insensitive (DI). A digital circuit is DI when its correct operation is independent of the delays in operators and in the wires connecting the operators, except that the delays are finite and positive.
KeywordsPartial Order Successor Relation Storage Element Defense Advance Research Project Agency Projection Theorem
Unable to display preview. Download preview PDF.