SPARC Implementations: ASIC vs. Custom Design

Abstract

The first two implementations of the SPARC architecture, MB86900 and CY7C601 were designed using high speed CMOS technology with processor clock speed in the range of 16.6 MHz to 33 MHz. In a system with a reasonable size external cache, these processors execute integer operations at a rate of approximately 1.5 clock cycles per instruction resulting in a sustained performance in the range of 10 to 20 MIPS. MB86900 design uses a single 20,000 gate 1.3 micron CMOS gate-array from Fujitsu and operates at a cycle time of 60ns. CY7C601, on the other hand, is a full custom chip designed using Cypress Semiconductor’s 0.8 micron CMOS process and operates at a cycle time of 30ns. In this paper we discuss the basic features of these processors, their similarities and differences and the trade-offs used in their design. We also address the issues of design verification, test generation and fault simulation.