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Implementation on Parallel Architectures

  • Richard Tolimieri
  • Myoung An
  • Chao Lu
Part of the Signal Processing and Digital Filtering book series (SIGNAL PROCESS)

Abstract

In this chapter, we will consider some issues surrounding parallel implementation of several MDFT algorithms on a broadcast mode multiprocessor machine. Such machines typically feature a collection of homogeneous processing elements (nodes) together with an interconnection network of a regular topology for interprocessor communication. The node processors are externally connected by a single I/O channel to a host through which all data loads and unloads are carried out (see Figure 11.1).

Keywords

Discrete Fourier Transform Processing Element Hybrid Algorithm Parallel Implementation Parallel Architecture 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 1997

Authors and Affiliations

  • Richard Tolimieri
    • 1
  • Myoung An
    • 2
  • Chao Lu
    • 3
  1. 1.Department of Electrical EngineeringCity College of CUNYNew YorkUSA
  2. 2.A.J. Devaney AssociatesAllstonUSA
  3. 3.Department of Computer and Information SciencesTowson State UniversityTowsonUSA

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