Abstract
A wide variety of DFT and convolution algorithms have been designed to optimize computations with respect to the number of arithmetic operations, especially multiplications. Blahut (1985) [1]offers an excellent survey of many algorithms designed using this methodology. Today, with the rapid advance in VLSI technology and the availability of high-speed and inexpensive floating-point processors, the time required to carry out a fixed-point addressing operation or a floating-point addition can effectively be the same as that for the floating-point multiplication. Some advanced architectures have these functional units working in parallel, with multiple operations realized in one or a few cycles at the same time. Traditional algorithm design of trading multiplications for additions, therefore, is not only ineffective but can result in a significant decrease in performance.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Blahut, R.E. (1985), Fast Algorithms For Digital Signal Processing, Addison-Wesley, Reading, MA.
Bogoch, S., Bason, I., Williams, J., and Russell, M. (1990), “Supercomputers Get Personal,” BYTE Magazine, 231–237.
Dewar, R.B. and Smosna, M. (1990), Microprocessors: A Programmer’s View, McGraw-Hill Publishing Co., New York.
Granata, J.A. (1990), The Design of Discrete Fourier Transform and Convolution Algorithms For RISC Architectures, Ph.D. dissertation, the City University of New York.
Hennessy, J.L. (1984), “VLSI Processor Architecture,” IEEE Computers C-33, 1221–1246.
Linzer, E. and Feig, E. (1991), “Implementation of Efficient FFT Algorithms on Fused Multiply-Add Architectures,” to appear.
Lu, C. (1991), “Implementation of ‘Multiply-Add’ FFT Algorithms for Complex and Real Data Sequences,” Proceeding of IEEE International Conference on Circuits and Systems, Singapore.
Lu C, Cooley, J.W., and Tolimieri, R. (1993),“FFT Algorithms for Prime Transform Sizes and Their Implementations on VAX, IBM 3090VF and RS/6000,” IEEE Trans. Signal Processing 41(2), February.
Lu C, Cooley, J.W., and Tolimieri, R. (1991), “Variants of the Winograd Multiplicative FFT Algorithms and Their Implementation on RS/6000,” Proceedings ICASSP-91, Toronto.
Lu, C, An, M., Qian, Z., and Tolimieri, R. (1992), “Small FFT module Implementation on the Intel i860 Processor,” Proc. ICSPAT, November, 2–5, Cambridge, MA.
Margulis, N. (1990), i860 Microprocessor Architecture, McGraw-Hill Publishing Co., New York.
Patterson, D.A. (1985), “Reduced Instruction Set Computers,” Communications of the ACM 28(1), 8–21.
Patterson, D.A. and Sequin, C.H. (1981), “RISC I: A Reduced Instruction Set VLSI Computer,” Proc. 8th Internat. Sympos. Computer Architectures ACM, 443–457.
Patterson, D.A. and Sequin, C.H. (1982), “A VLSI RISC,” IEEE Computer Mag., September, 8–22.
Radin, G. (1982), “The 801 Minicomputer,” Computer Architecture News 10, 39–47.
Stallings, W. (1990), Reduced Instruction Set Computers (RISC), Second Edition. IEEE Computer Society Press.
Tolimieri, R., An, M., and Lu, C. (1989), Algorithms for Discrete Fourier Transform and Convolutions, Springer-Verlag, New York.
IBM Journal of Research and Development: Special Issue on IBM RISC System/6000 Processor, June, 1990.
Intel, iPSC/860 Supercomputer Advanced Information Fact Sheet. Intel 1990.
AT&T DSP Parallel Processor BT-100 User Manual, AT&T, 1988.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1997 Springer Science+Business Media New York
About this chapter
Cite this chapter
Tolimieri, R., An, M., Lu, C. (1997). Implementation on RISC Architectures. In: Burrus, C.S. (eds) Mathematics of Multidimensional Fourier Transform Algorithms. Signal Processing and Digital Filtering. Springer, New York, NY. https://doi.org/10.1007/978-1-4612-1948-4_10
Download citation
DOI: https://doi.org/10.1007/978-1-4612-1948-4_10
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4612-7352-3
Online ISBN: 978-1-4612-1948-4
eBook Packages: Springer Book Archive