Linear Control Approaches for DC-DC Power Converters

Abstract

This chapter covers the topic of DC-DC power electronic converter control in continuous-conduction mode. It aims at presenting how converter averaged (low-frequency) behavior can be tailored by means of feedback control structures. There is no unique control paradigm that solves this problem. To this end, various control structures with different design methods that have become classical in control systems theory can be employed with a similar degree of efficiency. It is generally assumed that the obtained control input is applied to converter switches by using pulse-width modulation. This chapter aims at giving a comprehensive view of this topic without exhausting the entire range of control approaches dedicated to the subject. The chapter presents the main principles, the design procedures and provides some pertinent examples, ending with two case studies and a set of problems.

Problems

Problem 8.1

Cascaded-loop control of Watkins–Johnson converter

The converter in Fig. 8.34 has input supply voltage E = 24 V (constant), inductance L = 0.33 mH, parasitic series resistance R _L  = 0.1 Ω and output capacitor C = 2700 μF. This converter supplies a mainly resistive load R and has a rated power of 350 W. The control input is PWM and the converter is supposed to operate in ccm. The output voltage must follow a variable reference, which may vary between − 3E and + E. To this end, design a cascaded control structure like the one detailed in Sect. 8.3. The following points must be addressed:

Fig. 8.34

Two-loop cascaded control of a Watkins–Johnson converter

• (a) obtain the converter’s averaged model and study its steady-state behavior;

• (b) obtain the linearized model of the inner current plant around a conveniently chosen operating point and compute the parameters of a PI controller for this plant starting from an imposed set of performances (bandwidth and damping);

• (c) obtain the linearized model of the outer voltage plant around the same operating point, then compute the parameters of a PI controller for this plant based upon some imposed performance that ensures clear separation of dynamics within the two control loops;

• (d) discuss how the plant’s parameters vary when the operating point changes and propose solutions for dealing with this.

Solution

(a) The averaged model of the converter is

$$ \left\{\begin{array}{l}L\overset{\cdotp }{i_L}=\left(2\upalpha -1\right)E-\upalpha {v}_C-{R}_L{i}_L\hfill \\ {}C\overset{\cdotp }{v_C}=\upalpha {i}_L-{v}_C/R.\hfill \end{array}\right. $$

(8.38)

In steady state (current derivative zeroed in the first equation of (8.38)) and by neglecting inductor losses (i.e., R _L  = 0), one obtains that

$$ {v}_{Ce}=E\cdot \left(2{\upalpha}_e-1\right)/{\upalpha}_e, $$

a relation that describes the steady-state behavior and shows that the output voltage varies within the (−∞, E], being zero for α _e  = 0.5.

(b) Supposing that the control loop renders the voltage v _C slowly variable, this latter may be considered constant (at its reference v ^* _C ) from the current variation point of view. Therefore, the first equation of (8.38) becomes

$$ L\frac{d{i}_L}{ dt}=\left(2\upalpha -1\right)E-\upalpha {v}_C^{*}-{R}_L{i}_L. $$

By expressing the latter equation in variations around a quiescent operating point, one obtains the transfer function of the inner plant:

$$ {H}_{i_L\upalpha}(s)=\frac{\tilde{i_L}(s)}{\tilde{\upalpha}(s)}=\frac{2E-{v}_C^{*}}{R_L}\cdot \frac{1}{L/{R}_L\cdot s+1}. $$

(8.39)

By employing a PI controller one obtains a closed-loop inductor current behavior described by a transfer function like the one in (8.18), where K _C  = (2E − v ^* _C )/R _L and T _C  = L/R _L  = 3.3 ms. If it is supposed that v ^* _C  ∈ [−2E, E], the plant gain varies between E/R _L and 4E/R _L (according to relation (8.39)). The design operating point is the one corresponding to the smallest plant gain while at full load: v _Ce  ≡ v ^* _C  = − 2E = − 48 V, α _e  = 0.25 (inductor losses neglected), K _C  = E/R _L  = 240 A, R _e  = 6.6 Ω and i _Le  = − 29 A.

One imposes the inner closed-loop performances: T _0C  = T _C /5 = 0.66 ms and a damping of 0.8. Equations (8.19) give controller parameters values T _iC  = 0.9 ms and K _pC  = 0.007 A^− 1. Note that, as the output voltage reference changes, from –2E to E, the steady-state gain K _C decreases by a factor of four and the closed-loop bandwidth decreases by a factor of two. A prefilter with the time constant T _iC is inserted on the current reference in order to compensate the inner loop zero.

(c) Now, concerning the outer voltage loop, by zeroing the dynamic in the first equation of (8.38) one obtains (v _Ce  ≡ v ^* _C )

$$ \upalpha =\frac{E+{R}_L{i}_L}{2E-{v}_C^{*}}, $$

which is replaced in the second equation of (8.38), leading after linearization to

$$ \tilde{v_c}(s)=\frac{\left(E+2{R}_L{i}_{Le}\right){R}_e}{2E-{v}_C^{*}}\cdot \frac{1}{C{R}_es+1}\cdot \tilde{i_L}-\frac{R_e}{C{R}_es+1}\cdot \tilde{i_S}, $$

where $\tilde{i_S}=-{v}_C^{*}/{R}_e^2\cdot \tilde{R}$ is load current variation due to load variation $\tilde{R}$. As a consequence, the transfer function corresponding to the inductor-current-to-output-voltage channel is a first-order one

$$ {H}_{v{i}_L}(s)=\frac{\left(E+2{R}_L{i}_{Le}\right){R}_e}{2E-{v}_C^{*}}\cdot \frac{1}{C{R}_es+1}, $$

whose parameters – gain and time constant – depend on the operating point.

By using the same procedure as done for the inner loop, one may design the outer loop PI controller – see relations (8.20). In this case ${K}_V=\frac{\left(E+2{R}_L{i}_{Le}\right){R}_e}{2E-{v}_C^{*}}$ and T _V  = R _e C. For the same operating point as in the inner loop, one obtains K _V  = 1.45 V/A and T _V  = 17.8 ms. One imposes the outer closed-loop performances: T _0V  = T _V /5 = 3.6 ms and a damping of 0.8. Equations (8.20) give K _pV  = 4.83 A/V and T _iV  = 5 ms. Note that the ratio between the inner loop bandwidth and that of the outer loop is almost 5.4, which is satisfactory because it ensures the dynamics within the two nested loops are clearly separable. The voltage reference can be passed through a prefilter with time constant in order to compensate for the outer loop zero.

At this time the control design may be considered complete for the chosen operating point and one may proceed to closed-loop simulations.

(d) As regards change of steady-state operating point, this induces some degradation of the control performance. In our case variations of both load resistance and voltage reference represent causes of such degradation. Relations (8.18) and (8.19) show that for constant output voltage reference, closed-loop damping is slightly reduced for different load resistances R _e with respect to the imposed damping (0.8). Even more severe is the influence of the voltage reference change from –2E to E. The outer plant steady-state gain K _V increases by a factor of four and the outer closed-loop bandwidth increases by two. Meanwhile, the inner closed-loop bandwidth is halved. This leads to the ratio between inner and outer bandwidth being reduced to only 1.35, which is not sufficient to guarantee clear dynamics separation within the two nested loops. Obviously, this will lead to unwanted global behavior.

To avoid this kind of problem, one solution is to adopt an adaptive control that modifies in real time the controllers’ proportional gains, for example, by using a lookup table. Alternatively, one may use the following adaptation relations that alter the nominal proportional gain values:

$$ \begin{array}{cc}\hfill {K}_{pC}^{new}={K}_{pC}\frac{4E}{2E-{v}_C^f},\hfill & \hfill {K}_{pV}^{new}={K}_{pV}\frac{2E-{v}_C^f}{4E}\hfill \end{array}, $$

where K _pC and K _pV correspond to the precomputed values (in the chosen design operating point) and v ^f _C is the quiescent output voltage and may be obtained either by suitably filtering the capacitor voltage or by filtering the voltage reference (e.g., one may use the voltage prefilter output).

The reader is invited to solve the following problems.

Problem 8.2

Buck DC-DC Converter Output Voltage Tracking

A buck converter (see Fig. 2.10 in Chap. 2) having L = 0.5 mH, C = 680 μF, E = 72 V and a rated load value R = 10 Ω must output a controlled voltage between 15 and 48 V. The minimum load value that still corresponds to ccm is considered to be 1000 Ω.

It is required to design a voltage-mode (direct) control structure based upon a proportional-integral controller that ensures the largest bandwidth possible and a damping coefficient between 0.65 and 0.85, all by maintaining a phase margin of 30° for the entire output voltage operating range.

The controller must be implemented using a digital signal processor having a sampling rate of 20 kHz. Obtain the discrete transfer function of the controller and its associated difference equation.

Problem 8.3

Quadratic Buck DC-DC Converter Control Using Dynamic Compensation by Pole-placement

Figure 8.35 shows a quadratic buck power stage (also presented in Fig. 4.38 at the end of Chap. 4).

Fig. 8.35

Control structure of the quadratic buck DC-DC converter; PWM and gate driver omitted

The converter has the following circuit parameters: L ₁ = 0.5 mH, L ₂ = 0.5 mH, C ₁ = 470 μF, C ₂ = 1000 μF, E = 100 V and a rated load value R = 5 Ω. The control scope is to maintain a desired constant output voltage, v ^* _C2   = 15 V.

For this four-state converter, design a control structure based upon the dynamic compensation by pole-placement. Imposed control performance for the inner loop includes placement of the closed-loop dominant second-order dynamic at a bandwidth five times larger than the open-loop one and suitable damping coefficients (e.g., 0.8) for both second-order dynamics. Further, the integral gain in the outer regulation loop will be chosen by using the root locus method so as to ensure the maximal closed-loop bandwidth.

Problem 8.4

Ćuk Converter using Dynamic Compensation by Pole-placement

For the Ćuk converter presented in Fig. 3.17 at the end of Chap. 3, desired constant output voltage v ^* _C2  = 50V is aimed at. The circuit parameters are: L ₁ = 0.5 mH, L ₂ = 0.5 mH, C ₁ = 220 μF, C ₂ = 1000 μF, E = 100 V and a rated load value R = 2 Ω.

It is required to design a control structure based upon the dynamic compensation by pole-placement. The same global control structure and imposed closed-loop requirements as in the previous problem are considered.

Problem 8.5

Voltage Regulation Control of a Flyback Converter

A lossless flyback converter operating in continuous-conduction mode is considered (see Fig. 4.24 of Chap. 4), which must output constant voltage v ^* _C  = 3.3 V on a constant load R = 10 Ω, while its supply voltage varies between 0.5v ^* _C and 1.5v ^* _C . The circuit parameters are L = 0.22 mH and C = 2200 μF. Address the following points:

• (a) Design a two-loop control structure (averaged current-mode control) that ensures a 3-kHz-bandwidth of the voltage closed loop for the entire operating range.

• (b) Discretize the controllers obtained in part a and compute their digital counterparts for the sampling frequency f _s  = 40 kHz.

Problem 8.6

Power Factor Correction Using Boost DC-DC Converter Control

Let us consider the case of a resistive load R supplied by means of a diode voltage rectifier and a boost configuration, as presented in Fig. 8.36. Provided that parameters L, C and E are known and measures of inductor current i _L and output voltage v _C are available, the global control goal is to design a control structure ensuring that the load voltage v _C is regulated at the reference value v ^* _C , meanwhile reducing the harmonic content of the current absorbed from the grid i _S and ensuring operation at unit power factor.

Fig. 8.36

Single-phase rectifier with boost power stage

The design will be based upon a cascaded control structure having averaged current i _L as inner variable and averaged voltage v _C as outer variable (Rossetto et al. 1994). Figure 8.37 presents this control structure.

Fig. 8.37

Cascaded control structure ensuring unit-power-factor operation of the circuit in Fig. 8.36

Address the following issues:

• (a) explain how current reference i ^* _L is computed (where I _S is the amplitude of grid current i _S );

• (b) obtain the inner plant linearized model and choose a suitable controller structure;

• (c) knowing that the PWM switching frequency is f = 10 kHz and ω = 2π ⋅ 50 rad/s, suggest a pertinent way of imposing the inner closed-loop bandwidth, then compute the inner-loop controller;

• (d) obtain the outer plant linearized model and choose a suitable controller structure;

• (e) by requiring that the outer closed-loop bandwidth be one-tenth that of the inner loop, compute the outer-loop controller;

• (f) build and simulate in MATLAB^®-Simulink^® the block diagram corresponding to the nonlinear averaged model of the uncontrolled circuit for the following set of parameters: L = 2 mH, C = 1000 μF, E = 300 V and load R taking values in the interval [100 Ω, 10 kΩ];

• (g) by freezing the voltage v _C at its reference value v ^* _C  = 500 V and choosing the full-load operating point (R = 100 Ω) build and simulate the inner control loop – with the controller computed in part c – then validate the imposed dynamical performance;

• (h) build the outer-loop block diagram – with the controller computed in part e, simulate its behavior and validate the closed-loop performance for the full-load operating point;

• (i) move the entire controlled system around another operating point, e.g., R = 10kΩ, without modifying the previously computed controllers and simulate its behavior, then assess the control performance degradation;

• (j) propose an adaptation law for the outer-loop controller.