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Rapid Prototyping and Programming Multi-Core Architectures

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Physical Layer Multi-Core Prototyping

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 171))

Abstract

This chapter gives an over view of the existing work on rapid prototyping and multi-core deployment in the signal processing world. The concept of rapid prototyping was introduced in Fig. 1.2 when outlining the structure of this document. It consists of automatically generating a system simulation or a system prototype from quickly constructed models. Rapid prototyping may be used for several purposes; this study uses it to manage the parallelism of DSP architectures. Parallelism must be handled differently for the macroscopic or microscopic views of a system.

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References

  1. Davis AL, Stotzer EJ, Tatge RE, Ward AS (1996) Approaching peak performance with compiled code on a VLIW DSP. Proceedings of lCSPAT Fall

    Google Scholar 

  2. Lee E (2006) The problem with threads. Computer 39(5):33–42

    Article  Google Scholar 

  3. Lee EA, Parks TM (1995) Dataflow process networks. Proc IEEE 83(5):773–801

    Article  Google Scholar 

  4. International Technology Roadmap for Semiconductors (2009) I.T.R.: Design. www.itrs.net

  5. Karam LJ, AlKamal I, Gatherer A, Frantz GA, Anderson DV, Evans BL (2009) Trends in multicore DSP platforms. IEEE Signal Process Mag 26(6):38–49

    Article  Google Scholar 

  6. Heath S (1995) Microprocessor architectures RISC, CISC and DSP. Butterworth-Heinemann Ltd., Oxford

    Google Scholar 

  7. Tensilica. http://www.tensilica.com/

  8. Flynn MJ (1972) Some computer organizations and their effectiveness. IEEE Trans Comput 100:21

    Google Scholar 

  9. Blazewicz J, Ecker K, Plateau B, Trystram D (2000) Handbook on parallel and distributed processing. Springer, Berlin

    MATH  Google Scholar 

  10. Open SystemC initiative web site. http://www.systemc.org/home/

  11. Feiler PH, Gluch DP, Hudak JJ (2006) The architecture analysis and design language (AADL): an introduction. Technical report

    Google Scholar 

  12. Graham RL (1966) Bounds for certain multiprocessing anomalies. Bell Syst Tech J 45(9):1563–1581

    Google Scholar 

  13. Park H, Oh H, Ha S (2009) Multiprocessor SoC design methods and tools. IEEE Signal Process Mag 26(6):72–79

    Article  Google Scholar 

  14. Ceng J, Castrillon J, Sheng W, Scharwachter H, Leupers R, Ascheid G, Meyr H, Isshiki T, Kunieda H (2008) MAPS: an integrated framework for MPSoC application parallelization. In: Proceedings of the 45th annual conference on design automation, pp. 754–759

    Google Scholar 

  15. OpenMP. http://openmp.org/wp/

  16. Blumofe RD, Joerg CF, Kuszmaul BC, Leiserson CE, Randall KH, Zhou Y (1995) Cilk: an efficient multithreaded runtime system. In: Proceedings of the fifth ACM SIGPLAN symposium on principles and practice of parallel programming

    Google Scholar 

  17. OpenCL. http://www.khronos.org/opencl/

  18. The Multicore Association. http://www.multicore-association.org/home.php

  19. Kwon S, Kim Y, Jeun WC, Ha S, Paek Y (2008) A retargetable parallel-programming framework for MPSoC. ACM Trans Des Autom Electron Syst 13(3):39

    Article  Google Scholar 

  20. Ghenassia F (2006) Transaction-level modeling with systemC: TLM concepts and applications for embedded systems. Springer-Verlag New York, Inc. http://portal.acm.org/citation.cfm?id=1213675

  21. Hsu CJ, Keceli F, Ko MY, Shahparnia S, Bhattacharyya SS (2004) Dif: an interchange format for dataflow-based design tools. http://citeseerx.ist.psu.edu/viewdoc/summary? doi:10.1.1.76.6859

  22. Hsu, C.J., Ko, M.Y., Bhattacharyya, S.S.: Software synthesis from the dataflow interchange format. In: SCOPES ’05: Proceedings of the 2005 workshop on Software and compilers for embedded systems, pp. 37–49. ACM, New York, NY, USA (2005). http://doi.acm.org/10.1145/1140389.1140394

  23. Shen C, Plishker W, Wu H, Bhattacharyya SS (2010) A lightweight dataflow approach for design and implementation of SDR systems. In: Proceedings of the wireless innovation conference and product exposition, Washington DC, USA, pp. 640–645

    Google Scholar 

  24. Shen C, Wang L, Cho I, Kim S, Won S, Plishker W, Bhattacharyya SS (2011) The DSPCAD lightweight dataflow environment: introduction to LIDE version 0.1. Technical report UMIACS-TR-2011-17, Institute for Advanced Computer Studies, University of Maryland at College Park http://hdl.handle.net/1903/12147

  25. Stuijk S, Geilen M, Basten T (2006) SDF\(^3\): SDF For Free. In: Application of concurrency to system design, 6th international conference, ACSD 2006, proceedings. IEEE Computer Society Press, Los Alamitos, CA, USA pp. 276–278. http://www.es.ele.tue.nl/sdf3

  26. Theelen B (2007) A performance analysis tool for Scenario-Aware streaming applications. In: Fourth international conference on the quantitative evaluation of systems, QEST 2007, pp. 269–270. doi:10.1109/QEST.2007.7

  27. Lee E (2001) Overview of the ptolemy project. Technical memorandum UCB/ERL M01/11, University of California at Berkeley

    Google Scholar 

  28. Thies, W., Karczmarek, M., Gordon, M., Maze, D.Z., Wong, J., Hoffman, H., Brown, M., Amarasinghe, S.: Streamit: A compiler for streaming applications. Technical Report MIT/LCS Technical Memo LCS-TM-622, Massachusetts Institute of Technology, Cambridge, MA (2001). http://groups.csail.mit.edu/commit/papers/01/StreamIt-TM-622.pdf

  29. Grandpierre T, Sorel Y (2003) From algorithm and architecture specifications to automatic generation of distributed real-time executives: a seamless flow of graphs transformations. In: MEMOCODE ’03, pp. 123–132

    Google Scholar 

  30. Dahlin A, Ersfolk J, Yang G, Habli H, Lilius J (2009) The canals language and its compiler. In: Proceedings of th 12th international workshop on software and compilers for embedded systems, pp. 43–52

    Google Scholar 

  31. Bhattacharyya SS, Eker J, Janneck JW, Lucarz C, Mattavelli M, Raulet M (2009) Overview of the MPEG Reconfigurable Video Coding Framework. Springer journal of Signal Processing Systems, Special Issue on Reconfigurable Video Coding, 2009

    Google Scholar 

  32. ISO/IEC FDIS 23001–4: MPEG systems technologies—Part 4: Codec Configuration Representation (2009)

    Google Scholar 

  33. Eker J, Janneck J (2003) CAL Language Report. Technical Report, ERL Technical Memo UCB/ERL M03/48, University of California at Berkeley, 2003

    Google Scholar 

  34. Eker J, Janneck J, Lee E, Liu J, Liu X, Ludvig J, Neuendor S, Sonia E, Yuhong S (2003) Taming heterogeneity—the Ptolemy approach. In. Proceedings of the IEEE, vol. 91, 2003

    Google Scholar 

  35. Calvez JP, Isidoro D (1994) A codesign experience with the mcse methodology. In: CODES ’94: Proceedings of the 3rd international workshop on Hardware/software co-design, pp. 140–147. IEEE Computer Society Press, Los Alamitos, CA, USA, 1994

    Google Scholar 

  36. PolyCore Software Poly-Mapper tool. http://www.polycoresoftware.com/products3.php

    Google Scholar 

  37. Eker J, Janneck JW (2003) CAL Language Report. Technical report, ERL Technical Memo UCB/ERL M03/48, University of California at Berkeley, 2003

    Google Scholar 

  38. Bhattacharyya S, Brebner G, Eker J, Janneck J, Mattavelli M, von Platen C, Raulet M (2008) OpenDF—a dataflow toolset for reconfigurable hardware and multicore systems. SIGARCH Comput. Archit, News

    Google Scholar 

  39. Karsai G, Sztipanovits J, Ledeczi A, Bapty T (2003) Model-integrated development of embedded software. Proc IEEE 91(1):145–164. doi:10.1109/JPROC.2002.805824

    Google Scholar 

  40. Belanovic P (2006) An open tool integration environment for efficient design of embedded systems in wireless communications. Ph.D. thesis, Technischen Universitat Wien

    Google Scholar 

  41. Grandpierre T, Lavarenne C, Sorel Y (1999) Optimized rapid prototyping for real-time embedded heterogeneous multiprocessors. In: (CODES ’99) Proceedings of the Seventh International Workshop on, Hardware/Software Codesign, pp. 74–78, 1999

    Google Scholar 

  42. Stuijk S (2007) Predictable mapping of streaming applications on multiprocessors. Ph.D. thesis, Technische Universiteit Eindhoven

    Google Scholar 

  43. Piat J, Bhattacharyya SS, Pelcat M, Raulet M (2009) Multi-core code generation from interface based hierarchy. DASIP 2009

    Google Scholar 

  44. Lee EA (1989) Scheduling strategies for multiprocessor real-time DSP. In: IEEE global telecommunications conference and exhibition. Communications Technology for the 1990s and Beyond, 1989

    Google Scholar 

  45. Sriram S, Bhattacharyya SS (2009) Embedded multiprocessors: scheduling and synchronization, 2nd edn. CRC press, Boca Raton

    Google Scholar 

  46. Brucker P (2007) Scheduling algorithms. Springer, New York

    Google Scholar 

  47. Garey MR, Johnson DS (1990) Computers and intractability: a guide to the theory of NP-Completeness. W. H. Freeman& Co. (1990). http://portal.acm.org/citation.cfm?id=574848

  48. Cormen TH, Leiserson CE, Rivest RL, Stein C (2001) Introduction to algorithms, 2nd edn. The MIT Press, Cambridge

    Google Scholar 

  49. Kwok Y (1997) High-performance algorithms of compile-time scheduling of parallel processors. Ph.D. thesis, Hong Kong University of Science and Technology

    Google Scholar 

  50. Hu TC (1961) Parallel sequencing and assembly line problems. Oper Res 9(6):841–848

    Article  Google Scholar 

  51. Sinnen O (2007) Task scheduling for parallel systems (Wiley Series on Parallel and Distributed Computing). Wiley-Interscience, New York

    Google Scholar 

  52. Mu P (2009) Rapid prototyping methodology for parallel embedded systems. Ph.D. thesis, INSA Rennes

    Google Scholar 

  53. Radulescu A, van Gemund AJ (1999) On the complexity of list scheduling algorithms for distributed-memory systems. In: Proceedings of the 13th international conference on Supercomputing, pp. 68–75

    Google Scholar 

  54. Janecek TH (2003) Static vs. dynamic List-Scheduling performance comparison. Acta Polytech 43(6):23–28

    Google Scholar 

  55. Kwok YK, Ahmad I (1999) FASTEST: a practical low-complexity algorithm for compile-timeassignment of parallel programs to multiprocessors. IEEE Trans Parallel Distributed Syst 10(2):147–159

    Article  Google Scholar 

  56. Khandelia M, Bambha NK, Bhattacharyya SS (2006) Contention-conscious transaction ordering in multiprocessors DSP systems. In: IEEE Transactions on signal processing, 2006

    Google Scholar 

  57. Bhattacharyya SS, Sriram S, Lee EA (1997) Optimizing synchronization in multiprocessor DSP systems. IEEE Trans Signal Process 45(6):1605–1618

    Google Scholar 

  58. Bambha N, Kianzad V, Khandelia M, Bhattacharyya SS (2002) Intermediate representations for design automation of multiprocessor DSP systems. Des Autom Embed. Syst 7(4):307–323

    Google Scholar 

  59. Balarin F, Lavagno L, Murthy P, Sangiovanni-vincentelli A (1998) Scheduling for embedded real-time systems. IEEE Des Test Comput 15(1):71–82

    Google Scholar 

  60. Ha S, Lee EA (1997) Compile-time scheduling of dynamic constructs in dataflow program graphs. IEEE Trans Comput 46:768–778

    Google Scholar 

  61. Buck J, Ha S, Lee EA, Messerschmitt DG (1994) Ptolemy: A framework for simulating and prototyping heterogeneous systems. Int J Comput Simul 4(2):155–182

    Google Scholar 

  62. Boutellier J, Bhattacharyya SS, Silven O (2009) A low-overhead scheduling methodology for fine-grained acceleration of signal processing systems. J Signal Process Syst 57(2):121–122

    Google Scholar 

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Authors and Affiliations

  1. INSA Rennes, 20 Avenue des Buttes de Coësmes, CS 70839, 35708, Rennes Cedex 7, France

    Maxime Pelcat & Jean-François Nezan

  2. Texas Instruments, Avenue Jack Kilby 821, 06271, Villeneuve-Loubet, France

    Slaheddine Aridhi

  3. LAA/CNRS, Avenue du colnel roche 7, 31077, Toulouse, France

    Jonathan Piat

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  1. Maxime Pelcat
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  2. Slaheddine Aridhi
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  3. Jonathan Piat
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  4. Jean-François Nezan
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Pelcat, M., Aridhi, S., Piat, J., Nezan, JF. (2013). Rapid Prototyping and Programming Multi-Core Architectures. In: Physical Layer Multi-Core Prototyping. Lecture Notes in Electrical Engineering, vol 171. Springer, London. https://doi.org/10.1007/978-1-4471-4210-2_4

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  • DOI: https://doi.org/10.1007/978-1-4471-4210-2_4

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  • Online ISBN: 978-1-4471-4210-2

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