Abstract
Asynchronous circuit design is a beautiful application area for any formalism that can reason about parallelism By means of two small, but challenging, exercises we illustrate the similarities and differences between parallel program and asynchronous circuit design. The exercises are simple to state and have many solutions, which are sometimes surprisingly efficient. They all illustrate many aspects of asynchronous circuit design. For each exercise we present several solutions, which are analysed with respect to delay assumptions, safety, progress, and performance issues. We also mention some open problems.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
C.H. van Berkel, Handshake Circuits: An Intermediary between Communicating Processes and VLSI. PhD Thesis, Dept. of Mathematics and Computing Science, Eindhoven University of Technology, 1992.
K. van Berkel, VLSI Programming of a Modulo-N Counter with Constant Response Time and Constant Power, in: S. Furber and M. Edwards eds., Asynchronous Design Methodologies, IFIP Transactions A-28, North-Holland, 1993, 1–12.
G.M. Brown, Towards Truly Delay-insensitive Circuit Realizations of Process Algebras, in: G. Jones and M. Sheeran eds., Designing Correct Circuits, Workshops in Computing, Springer Verlag, Berlin, 1990, 120–131.
J.A. Brzozowski and C-J.H. Seger, A Unified Framework for Race Analysis of Asynchronous Networks, J. ACM, 36 (1), 1989, 20–45.
S. Burns and A.J. Martin, Performance Analysis and Optimization of Asynchronous Circuits, in: Carlo H. Sequin ed., Advanced Research in VLSI, MIT Press, Cambridge, Mass., 1991, 71–86.
W. Chen, J.T. Udding, and T. Verhoeff, Networks of Communicating Processes and Their (De-)Composition, in: J.L.A. van de Snepscheut ed., Mathematics of Program Construction, Lecture Notes in Computer Science 375, Springer-Verlag, Berlin, 1989, 174–196.
W.A. Clark, Macromodular Computer Systems, in: Proceedings of the Spring Joint Computer Conference, AFIPS, Academic Press, London, 1967, 335–401.
A. Davis, B. Coates, K. Stevens, Automatic Synthesis of Fast Compact Self-Timed Control Circuits, in: S. Furber and M. Edwards eds., Asynchronous Design Methodologies, IFIP Transactions A-28, North-Holland, Amsterdam, 1993, 193–208.
A. Davis, B. Coates, K. Stevens, The Post Office Experience: Designing a Large Asynchronous Chip, in T.N. Mudge et al. eds., Proceedings of the 26th Annual Hawaii International Conference on System Sciences, Vol. 1, IEEE Computer Society Press, 1993, 409–418.
E.W. Dijkstra, A Discipline of Programming, Prentice-Hall, 1976.
D.L. Dill, Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits, MIT Press, Cambridge, Mass., 1989.
J.C. Ebergen, A Formal Approach to Designing Delay-Insensitive Circuits, Distributed Computing, 5 (3), 1991, 107–119.
J.C. Ebergen and A.M.G. Peeters, Modulo-N Counters: Design and Analysis of Delay-Insensitive Circuits, in: J. Staunstrup and R. Sharp eds., Designing Correct Circuits, IFIP Transactions A-5, North-Holland, Amsterdam, 1992, 27–46.
L.J. Guibas and F.M. Liang, Systolic Stacks, Queues, and Counters, in: P. Penfield Jr. ed., Advanced Research in VLSI, Artech House, 1982, 155–164.
C.A.R. Hoare, Communicating Sequential Processes, Prentice-Hall, London, 1985.
H. Hulgaard, S. Burns, T. Amon, and Gaetano Borriello, An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems, Technical Report 94–02–02, Department of Computer Science and Engineering, University of Washington, Seattle, 1994.
E.V. Jones and G. Bi, Fast Up/Down Counters Using Identical Cascaded Modules, IEEE Journal of Solid-State Circuits, 23 (1), 1988, 283–285.
M.B. Josephs and J.T. Udding, Delay-Insensitive Circuits: An Algebraic Approach to Their Design, in: J.C.M. Baeten and J.W. Klop eds., CONCUR 1990, Lecture Notes in Computer Science 458, Springer-Verlag, Berlin, 1990, 342–366.
J.L.W. Kessels, Designing Counters with Bounded Response Time, in: W.H.J. Feijen and A.J.M. van Gasteren eds., C.S. Scholten Dedicata: van oude machines en nieuwe rekenwijzen, Academic Service, Schoonhoven, 1990, 127–140.
L. Lavagno and A. Sangiovanni-Vincentelli, Algorithms for Synthesis and Testing of Asynchronous Circuits, Kluwer Academic Press, 1993.
X.D. Lu and P.C. Treleaven, A Special-Purpose VLSI Chip: A Dynamic Pipeline Up/Down Counter. Microprocessing and Microprogramming, 10 (1), 1982, 1–10.
A.J. Martin, Programming in VLSI: From Communicating Processes to Delay-Insensitive Circuits, in: C.A.R. Hoare ed., Developments in Con-currency and Communication, Addison-Wesley, Reading, Mass., 1990, 164.
C.E. Molnar, T.P. Fang and F.U. Rosenberger, Synthesis of Delay-Insensitive Modules, in: H. Fuchs ed., 1985 Chapel Hill Conference on VLSI, Computer Science Press, Rockville, Maryland, 1985, 67–86.
R.E. Miller, Switching Theory, Vol. 2, Chapter 10, Wiley, New York, 1965, 199–244.
S.M. Nowick and D.L. Dill, Synthesis of Asynchronous State Machines Using a Local Clock, Proceedings of the 1991 IEEE International Conference on Computer Design: VLSI in Computers and Processors, IEEE Computer Society Press, 1991, 192–197.
R.M.M. Oberman, Counting and Counters, Macmillan Press, 1981.
B. Parhami, Systolic Up/Down Counters with Zero and Sign Detection, in: M.J. Irwin and R. Stefanelli eds., IEEE Symposium on Computer Arithmetic, IEEE Computer Society Press, 1987, 174–178.
M. Rem, Trace Theory and Systolic Computations, in: J.W. de Bakker, A.J. Nijman and P.C. Treleaven eds., PARLE, Parallel Architectures and Languages Europe, Vol. 1, Springer-Verlag, Berlin, 1987, 14–34.
F.U. Rosenberger, C.E. Molnar, T.J. Chaney, T.-P. Fang, Q-Modules: Internally Clocked Delay-Insensitive Modules, IEEE Trans. on Comp., C37, No. 9, 1988, pp. 1005–1018.
J.P.L. Segers, The Design and Analysis of Asynchronous Up-Down Counters, Research Report CS-93–29, Computer Science Department, University of Waterloo, 1993.
J. Sparso and J. Staunstrup, Design and Performance Analysis of Delay-Insensitive Multi-Ring Structures, in: T.N. Mudge et al. eds., 26th Annual Hawaii International Conference on System Sciences, Vol. 1, IEEE Computer Society Press, 1993, 349–358.
Jan L.A. van de Snepscheut, Trace Theory and VLSI Design,Lecture Notes in Computer Science 200, Springer-Verlag, 1985.
I.E. Sutherland, Micropipelines, Communications of the ACM, 32 (6), 1989, 720–738.
Alan M. Turing, Lecture to the London Mathematical Society on 20 February 1947. In: Carpentar BE, Doran RW eds., Charles Babbage Institute Reprint Series for the History of Computing, vol. 10, MIT Press, Cambridge, Massachusetts, 1986.
J.T. Udding, A Formal Model for Defining and Classifying Delay-Insensitive Circuits and Systems, Distributed Computing, 1 (4), 1986, 197204.
N.H.E. Weste and K. Eshragian, Principles of CMOS VLSI Design, Addison-Wesley, 1985.
T.E. Williams, Analyzing and Improving Latency and Throughput in Self-Timed Rings and Pipelines, Proceedings of 1992 ACM/SIGDA Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Princeton University, March 1992.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1995 Springer-Verlag London
About this paper
Cite this paper
Ebergen, J.C., Segers, J., Benko, I. (1995). Parallel Program and Asynchronous Circuit Design. In: Birtwistle, G., Davis, A. (eds) Asynchronous Digital Circuit Design. Workshops in Computing. Springer, London. https://doi.org/10.1007/978-1-4471-3575-3_2
Download citation
DOI: https://doi.org/10.1007/978-1-4471-3575-3_2
Publisher Name: Springer, London
Print ISBN: 978-3-540-19901-4
Online ISBN: 978-1-4471-3575-3
eBook Packages: Springer Book Archive