Abstract
This paper is an examination of some issues in domain ontology and of various knowledge representation techniques for the temporal modelling of digital electronic circuits in Prolog. It should serve as an example of the advantages of such analysis, an area of relative neglect within the logic programming community.
Describing the standard technique for modelling circuits in Prolog, the representation of consecutive values on circuit ports is analyzed. An example, quoted from Clocksin [Clocksin 87], is shown to impede com-positionality by using different representations for input and output.
A range of possible time representations in this context is then given. One extreme of this range is a list of values, which is an analogical representation where time is implicit. The other end is a set of time-stamped events, which is a Fregean representation with explicit time. Two exam¬ples which exploit the Fregean representations are described: an event-driven simulator and a test vector generator.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Breuer, M. A. and Friedman, A. D. Diagnostics and Reliable Design of Digital Systems, Computer Science Press.
Broda, K. and Gregory, S. “Parlog For Discrate Event Simulation”, in Proceedings of The International Logic Programming Conference, Upsala, July 1984.
Bundy, A. and Welham, R. K. “Using Meta-Level Inference for Selective Application of Multiple Rewrite Rules”, in Algebraic Manipulation, AI Journal 16 pp 189 –212, 1981.
Clocksin, W. F. “Logic Programming and Circuit Analysis”, in Journal of Logic Programming, March 1987.
Futo, I. and Szeredi, J. “A Discrete Simulation System Based on Artificial Intelligence Methods”, in Discrete Simulation and Related Fields, ed. Javor, A., North-Holland, 1982.
Gupta, A. and Welham, R. K. “Functional Test Generation for Digital Circuits”, in Proceedings of AIENG-88, Palo Alto, August, 1988.
Hayes, P. J. “Some Problems and non-Problems in Representation Theory”, in Proceedings of AISB Summer Conference, University of Sussex, July 1974.
Kowalski, R. Logic for Problem Solving, pp 120 –121, North Holland, 1979.
Mackinlay, J. and Genesereth, M. R. “Expressiveness and Language Choice”, in Data and Knowledge Engineering, Vol. 1, pp 17 –29, North-Holland, 1985.
Roth, J. P., Bouricius, W. G. and Schneider, P. R. “Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits”, in IEEE Transactions on Electronic Computers, Vol 1. EC-16, No.5, pp 567 –580, October, 1967.
Sloman, A. The Computer Revolution in Philosophy, The Harvester Press, 1978.
Suzuki, N. “Concurrent Prolog as an Efficient VLSI Design Language”, in IEEE Computer, February 1985.
The TTL Data Book, Texas Instruments, 1978.
Weinbaum, D. and Shapiro, E. “Hardware Description and Simulation Using Concurrent Prolog”, in Concurrent Prolog — Collected Papers, ed. Shapiro, E., MIT Press, 1987.
Welham, R. K. “Declaratively Programmable Interpreters and Meta-Level Inference”, in Meta-Level Architectures and Reflection, eds. Mares, P. and Nardi, D., North Holland, 1988.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1992 Springer-Verlag London
About this paper
Cite this paper
Lichtenstein, Y., Welham, B., Gupta, A. (1992). Time Representation in Prolog Circuit Modelling. In: Wiggins, G.A., Mellish, C., Duncan, T. (eds) ALPUK 91. Workshops in Computing. Springer, London. https://doi.org/10.1007/978-1-4471-3546-3_5
Download citation
DOI: https://doi.org/10.1007/978-1-4471-3546-3_5
Publisher Name: Springer, London
Print ISBN: 978-3-540-19734-8
Online ISBN: 978-1-4471-3546-3
eBook Packages: Springer Book Archive