Parallel Frame Synchronous Scrambling

Abstract

In the parallel frame synchronous scrambling (PFSS), the parallel input data bitstreams are scrambled before multiplexing, and the scrambled data bitstream is descrambled after demultiplexing. In this chapter, we discuss the behaviors of parallel scrambling sequences for use in the parallel scrambling in view of the sequence space theory developed in Chapter 4, and consider how to realize SRGs generating parallel scrambling sequences using the SRG theory developed in Chapter 5. We will first show that the parallel scrambling sequences are the decimated sequences of the serial scrambling sequence. Then, we will discuss how to decompose the serial sequence into a linear sum of the so-called irreducible sequence and power sequence, and consider how to determine the decimated sequences of the irreducible and power sequences. We will also examine how to obtain the decimated sequences of the original serial sequences decomposed into the irreducible and power sequences. Finally, we will discuss how to realize parallel SRGs to generate parallel sequences, and consider how to achieve their minimal realizations.