Introduction to Self Synchronous Scrambling

Abstract

Self synchronous scrambling (SSS) is a scrambling technique which employs a kind of SRGs for use in scrambling as well as in descrambling of data bitstream. The transmission data stream is scrambled by passing through a scrambler composed of shift register generators and exclusive-OR gates, and the scrambled signal is descrambled by passing through a descrambler which is the same as the scrambler but the input and the output are reversed. In the SSS, the states of the scrambler and descrambler shift registers are automatically synchronized without any additional synchronization process. Scrambling effect of the SSS is good in general, but a bit error in the scrambled bitstream can cause multibit errors after descrambling. For the SSS, parallel scrambling techniques are available in the multiplexed environment, as for the FSS and the DSS. However, differently from these two cases, the parallel SSS (PSSS) can be applied to the parallel input signals without requiring any overlaid multiplexing frame. Instead, it requires an appropriate means to properly align the order of the descrambled parallel output signals.