Abstract
This work is aimed at designing a Phase Locked Loop (PLL) circuit to be used as a frequency synthesizer in a RF transceiver. In modern wireless communication systems the local oscillator phase noise specification sets the allowed strength of nearby channels. In the receiver (Figure 1), the PLL frequency f lo is set to a fixed offset from the desired channel fRF to downconvert it to the intermediate frequency f if .
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© 2000 Springer-Verlag London Limited
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Copani, T. (2000). BiPMOS Fractional-N Frequency Synthesizer For Wideband Wireless Systems. In: Fortuna, L., Ferla, G., Imbruglia, A. (eds) Microelectronics and Microsystems. Springer, London. https://doi.org/10.1007/978-1-4471-0671-5_1
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DOI: https://doi.org/10.1007/978-1-4471-0671-5_1
Publisher Name: Springer, London
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