Chapters 4 to 7 introduced the issues involved in designing an asynchronous SoC bus. A complete bus was then proposed in Chapter 8 and shown in the context of the AMULET3H subsystem. This chapter presents some of the post-layout simulations performed to validate the functionality of MARBLE and to measure its performance.
KeywordsResponse Channel Delay Distribution Read Latency Address Decoder Initiator Identifier
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