Abstract
Chapters 4 to 7 introduced the issues involved in designing an asynchronous SoC bus. A complete bus was then proposed in Chapter 8 and shown in the context of the AMULET3H subsystem. This chapter presents some of the post-layout simulations performed to validate the functionality of MARBLE and to measure its performance.
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© 2002 John Bainbridge
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Bainbridge, J. (2002). Evaluation. In: Asynchronous System-on-Chip Interconnect. Distinguished Dissertations. Springer, London. https://doi.org/10.1007/978-1-4471-0189-5_9
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DOI: https://doi.org/10.1007/978-1-4471-0189-5_9
Publisher Name: Springer, London
Print ISBN: 978-1-4471-1112-2
Online ISBN: 978-1-4471-0189-5
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