Applying Multi-Paradigm and Design Pattern Approaches to Hardware/Software Design and Reuse

Abstract

It is now feasible to manufacture chips having 100 M transistors. This is leading to the adoption of SOC (System-On-a-Chip) designs. Complexity, timeto-market pressure and evolving requirements push SOC design to reuse IP (Intellectual Property) blocks and build around programmable platforms. By opposition to the ASICs (Application Specific Integrated Circuits) where all the desired functionality is hardwired, programmable platforms contain programmable devices (such as processors) and specific functions are hardwired to meet some performance requirements; programmability offers flexibility, easy extensibility and adaptability to new requirements. This results in new challenges in the design process. Higher levels of abstraction must be defined. Description languages must handle both hardware and software components, and must be able to capture constraints and describe communication between them. CAD (Computer-Aided-Design) tools must allow integration of IP blocks, HW/SW (hardware/software) partitioning and communication mapping to obtain the expected performance. And finally verification must handle integrated hardware and software modules.