kHz-Rate Neural Processors

  • Dejan Marković
  • Robert W. Brodersen
  • Sarah Gibson
  • Vaibhav Karkare
Part of the Electrical Engineering Essentials book series (EEE)


This chapter presents a design example of a kHz-rate neural processor. A brief introduction to kHz design will be provided, followed by an introduction to neural spike sorting. Several spike-sorting algorithms will be reviewed. Lastly, the design of a 130-μW, 64- channel spike-sorting DSP chip will be presented.


Discrete Wavelet Transform Spike Detection Discrete Derivative Spike Sorting Sleep Transistor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media New York 2012

Authors and Affiliations

  • Dejan Marković
    • 1
  • Robert W. Brodersen
    • 2
  • Sarah Gibson
    • 3
  • Vaibhav Karkare
    • 3
  1. 1.Electrical Engineering DepartmentUniversity of California, Los AngelesLos AngelesUSA
  2. 2.Berkeley Wireless Research CenterUniversity of California, BerkeleyBerkeleyUSA
  3. 3.University of CaliforniaLos AngelesUSA

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