Abstract
Electro-migration (EM) in through-silicon-vias (TSVs) could become a serious design issue for TSVs having regions of high current density. In these regions, grain boundaries play a large role in EM dominating atomic transport. The focus of this chapter is to study EM in a comprehensive mutli-physics context including atomic transport due to grain boundaries. Atomic concentration and its time evolution is modeled. Our simulations show how voids and hillocks evolve in a TSV due to current crowding. We also investigate the impact of current, temperature, and various grain sizes on the EM reliability. These results and discussions provide guidance for designers to better understand and avoid EM reliability failures in 3D ICs.
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Lim, S.K. (2013). Modeling of Atomic Concentration at the Wire-to-TSV Interface. In: Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9542-1_9
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DOI: https://doi.org/10.1007/978-1-4419-9542-1_9
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