Abstract
In this chapter, we study an efficient chip/package thermo-mechanical stress and reliability co-analysis tool for TSV-based 3D ICs. We also study a design optimization methodology to alleviate mechanical reliability issues in 3D IC. First, we analyze the stress induced by chip/package interconnect elements, i.e., TSV, μ-bump, and package bump. Second, we explore and validate the principle of lateral and vertical linear superposition of stress tensors (LVLS), considering all chip/package elements. This linear superposition principle is utilized to perform full-chip/package-scale stress simulations and reliability analysis. Finally, we study the mechanical reliability issues in practical 3D chip/package designs including wide-I/O and block-level 3D ICs.
The materials presented in this chapter are based on [6].
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
K. Athikulwongse, A. Chakraborty, J.-S. Yang, D.Z. Pan, S.K. Lim, Stress-driven 3D-IC placement with TSV keep-out zone and regularity study, in Proceedings of IEEE International Conference on Computer-Aided Design, San Jose, 2010
G.V. der Plas et al., Design issues and considerations for low-cost 3D TSV IC technology, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, 2010
M.A. Hopcroft, W.D. Nix, T.W. Kenny, What is the Young’s modulus of silicon. J. Microelectromech. Syst. 19, 229–238 (2010)
M. Jung, X. Liu, S.K. Sitaraman, D.Z. Pan, S.K. Lim, Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC, in Proceedings of IEEE International Conference on Computer-Aided Design, San Jose, 2011
M. Jung, J. Mitra, D.Z. Pan, S.K. Lim, TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC, in Proceedings of ACM Design Automation Conference, San Diego, 2011
M. Jung, D. Pan, S.K. Lim, Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs, in Proceedings of ACM Design Automation Conference, San Francisco, 2012
J.-S. Kim et al., A 1.2 V 12.8 GB/s 2 Gb mobile wide-I/O DRAM with 4x128 I/O using TSV-based stacking, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, 2011
K.H. Lu, S.-K. Ryu, J. Im, R. Huang, P.S. Ho, Thermomechanical reliability of through-silicon vias in 3D interconnects, in IEEE International Reliability Physics Symposium, Monterey, 2011
M. Nakamoto et al., Simulation methodology and flow integration for 3D IC stress management, in Proceedings of IEEE Custom Integrated Circuits Conference, San Jose, 2010
S.R. Vempati et al., Development of 3-D silicon die stacked package using flip chip technology with micro bump interconnects, in IEEE Electronic Components and Technology Conference, San Diego, 2009
J. Zhang et al., Modeling thermal stresses in 3-D IC interwafer interconnects. IEEE Trans. Semicond. Manuf. 19, 437 (2006)
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer Science+Business Media New York
About this chapter
Cite this chapter
Lim, S.K. (2013). Chip/Package Co-analysis of Mechanical Stress for 3D IC. In: Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9542-1_15
Download citation
DOI: https://doi.org/10.1007/978-1-4419-9542-1_15
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4419-9541-4
Online ISBN: 978-1-4419-9542-1
eBook Packages: EngineeringEngineering (R0)