Chip/Package Co-analysis of Mechanical Stress for 3D IC
In this chapter, we study an efficient chip/package thermo-mechanical stress and reliability co-analysis tool for TSV-based 3D ICs. We also study a design optimization methodology to alleviate mechanical reliability issues in 3D IC. First, we analyze the stress induced by chip/package interconnect elements, i.e., TSV, μ-bump, and package bump. Second, we explore and validate the principle of lateral and vertical linear superposition of stress tensors (LVLS), considering all chip/package elements. This linear superposition principle is utilized to perform full-chip/package-scale stress simulations and reliability analysis. Finally, we study the mechanical reliability issues in practical 3D chip/package designs including wide-I/O and block-level 3D ICs.
The materials presented in this chapter are based on .
KeywordsDevice Layer Mechanical Reliability Background Stress Package Substrate Underfill Material
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