Abstract
In this chapter, we study the impact of through-silicon-via (TSV) and shallow trench isolation (STI) stress on the timing variations of 3D IC. We also study systematic TSV-STI-stress-aware timing analysis and show how to optimize layouts for better performance. First, we generate a stress contour map with an analytical radial stress model for TSV. We also develop a stress model for STI from finite element analysis (FEA) results. Then, depending on geometric relation between TSVs, STIs, and transistors, the tensile and compressive stresses are converted to hole and electron mobility variations. Mobility-variation-aware cell library and netlist are generated and incorporated into an industrial engine for timing analysis of 3D IC. We observe that TSV stress and STI stress interact with each other, and rise and fall time react differently to stress and relative locations with respect to both TSVs and STIs. Overall, TSV-STI-stress-induced timing variations can be as much as ± 15 % at the cell level. Thus, as an application to layout optimization, we exploit the stress-induced mobility enhancement to improve performance of 3D ICs. We show that stress-aware layout perturbation could reduce cell delay by up to 23.37 % and critical path delay by 6.67 % in our test case.
The materials presented in this chapter are based on [21].
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Notes
- 1.
The devices in 3D ICs may experience additional timing changes from process variations. The combined effect of stress and process variations on circuit timing is out of the scope of this chapter.
- 2.
Consideration of other stress enhancement methods such as SiGe is out of the scope of this chapter.
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Lim, S.K. (2013). Impact of Mechanical Stress on Timing Variation for 3D IC. In: Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9542-1_14
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DOI: https://doi.org/10.1007/978-1-4419-9542-1_14
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