Abstract
The convergence of wireless and semiconductor industries will turn into reality the vision of fully autonomous and seamless wireless connectivity in the near future, via combining advanced nanoscale CMOS technologies with innovative hybrid-domain circuits and systems solutions [1, 2]. One aim inside this immense scope is to develop a smart-mobile-companion device with high performance, adaptive connectivity and high power efficiency. High performance is the essential ingredient to cope with the ever increasing add-on of functionalities in a small handheld device. Adaptive connectivity is to automatically select the best wireless link, maximizing the quality of service wherever and whenever possible. Power efficiency is to extend the active-use days without entailing a big battery, or worrying about the battery life after executing much of the device’s functionality. To reach these three goals the system chips consisting of many analog and radio frequency (RF) circuits play a key role. The aim of adaptive connectivity promotes a full integration of many different radio technologies such as WiFi, Global Positioning System (GPS), BluetoothTM, cellular and mmWave into one unit, calling for an unprecedented high level of complexity among system planning, architectures and circuits. The goal of maximizing hardware sharing without compromising the performances challenges the designers throughout the front-to-back-end development. Yet, advanced nanoscale CMOS technology constitutes, still today, the most promising platform of wireless products for its tremendous advance in speed, system-on-chip capability and maturity (to some extent).
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Mak, PI., Martins, R.P. (2012). Introduction. In: High-/Mixed-Voltage Analog and RF Circuit Techniques for Nanoscale CMOS. Analog Circuits and Signal Processing. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9539-1_1
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DOI: https://doi.org/10.1007/978-1-4419-9539-1_1
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