Abstract
The MOSFETs in a silicon-on-insulator (SOI) technology are delineated in a thin silicon film, electrically isolated from the bulk silicon substrate by an oxide layer. CMOS circuits fabricated on an SOI substrate have inherent low parasitic source and drain junction capacitance and hence a potential for achieving higher switching speeds relative to circuits fabricated on bulk silicon. Because of electrical isolation and a smaller device volume, the circuits have higher immunity to latch up and to soft errors generated by incident radiation. In partially depleted silicon-on-insulator (PD-SOI) technology, electrical isolation of the MOSFET body from the underlying silicon substrate facilitates modulation of the threshold voltage, providing an opportunity for further circuit performance gain.
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Bhushan, M., Ketchen, M.B. (2011). Test Structures for SOI Technology. In: Microelectronic Test Structures for CMOS Technology. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9377-9_8
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DOI: https://doi.org/10.1007/978-1-4419-9377-9_8
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