Skip to main content

Fault Tolerance in BiNoC

  • Chapter
  • First Online:
Book cover Reconfigurable Networks-on-Chip

Abstract

For fault-tolerant data-link connections, a novel Bi-directional Fault-Tolerant NoC (BFT-NoC) scheme that supports both static and dynamic channel failures is proposed in this chapter. Except for a little performance loss, BFT-NoC can keep the system in normal operation when multiple communication channels are either permanently broken or temporarily failed in an on-chip network. In contrast to the conventional fault-tolerant schemes based on detouring packets, the operation of BFT-NoC is transparent to the adopted routing algorithm. That is, BFT-NoC can be more seamless and efficient since changing routing rules between normal and fault-tolerant operation modes is needless. Accordingly, it is possible for BFT-NoC to perform better in both resource utilization and application feasibility compared with other detour-based schemes.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 139.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. T. Schonwald, J. Zimmermann, O. Bringmann, and W. Rosentiel, “Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures,” in Proceedings of the Euromicro Conference on Digital System Design, pp. 527–534, August 2007

    Google Scholar 

  2. Z. Zhen, A. Greiner, and S. Taktak, “A Reconfigurable Routing Algorithm for a Fault-tolerant 2D-Mesh Network-on-Chip,” in Proceedings of the Design Automation Conference, pp. 441–446, June 2008

    Google Scholar 

  3. D. Fick, A. DeOrio, G. Chen, V. Bertacco, D. Sylvester, and D. Blaauw, “A Highly Resilient Routing Algorithm for Fault-Tolerant NoCs,” in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pp. 21–26, April 2009

    Google Scholar 

  4. M. Valinataj, S. Mohammadi, J. Plosila, and P. Liljeberg, “A Fault-Tolerant and Congestion-Aware Routing Algorithm for Networks-on-Chip,” in Proceedings of the IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, pp. 139–144, April 2010

    Google Scholar 

  5. A. Kohler, G. Schley, and M. Radetzki, “Fault Tolerant Network on Chip Switching With Graceful Performance Degradation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 6, pp. 883–896, June 2010

    Google Scholar 

  6. M. H. Cho, M. Lis, K. S. Shim, M. Kinsy, T. Wen, and S. Devadas, “Oblivious Routing in On-Chip Bandwidth-Adaptive Networks,” in Proceedings of the Parallel Architectures and Compilation Techniques, pp. 181–190, September 2009

    Google Scholar 

  7. Y. C. Lan, S. H. Lo, Y. C. Lin, Y. H. Hu, and S. J. Chen, “BiNoC: A Bidirectional NoC Architecture with Dynamic Self-Reconfigurable Channel,” in Proceedings of the International Symposium on Network-on-Chip, pp. 266–275, May 2009

    Google Scholar 

  8. L. Benini and G. DeMicheli, “Networks on Chips: a New SoC Paradigm,” IEEE Transactions on Computers, vol. 35, no. 4, pp. 70–78, January 2002

    Google Scholar 

  9. G. DeMicheli and L. Benini, Networks on Chips: Technology and Tools, Morgan Kaufmann, 2006

    Google Scholar 

  10. G. M. Chiu, “The Odd-Even Turn Model for Adaptive Routing,” IEEE Transactions on Parallel and Distributed Systems, vol. 11, no. 7, pp. 729–738, July 2000

    Google Scholar 

  11. G. Michelogiannakis, D. Sanchez, W. J. Dally, and C. Kozyrakis, “Evaluating Bufferless Flow Control for On-Chip Networks,” in Proceedings of the International Symposium on Networks-on-Chip, pp. 9–16, May 2010

    Google Scholar 

  12. S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS,” IEEE Transactions on Solid-State Circuits, vol. 43, no.1, pp. 29–41, January 2008

    Google Scholar 

  13. R. Dick, “Embedded System Synthesis Benchmark Suites (E3S),” http://ziyang.eecs.umich.edu/~dickrp/e3s/, Accessed January 2011

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Sao-Jie Chen .

Rights and permissions

Reprints and permissions

Copyright information

© 2012 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Chen, SJ., Lan, YC., Tsai, WC., Hu, YH. (2012). Fault Tolerance in BiNoC. In: Reconfigurable Networks-on-Chip. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9341-0_8

Download citation

  • DOI: https://doi.org/10.1007/978-1-4419-9341-0_8

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4419-9340-3

  • Online ISBN: 978-1-4419-9341-0

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics