Power Modeling and Reduction of VLIW Processors

  • Weiping Liao
  • Lei He

Abstract

In this chapter, we first present a cycle-accurate power simulator based on the IMPACT toolset. This simulator allows a designer to evaluate both VLIW compiler and micro-architecture innovations for power reduction. Using this simulator, we then develop and compare the following techniques with a bounded performance loss of 1% compared to the case without any dynamic throttling: (i) clock ramping with hardware-based prescan (CRHP), and (ii) clock ramping with compiler-based prediction (CROP). Experiments using SPEC2000 floating point benchmarks show that the power consumed by floating point units can be reduced by up to 31% and 37%, in CRHP and CROP respectively.

Keywords

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Copyright information

© Springer Science+Business Media New York 2003

Authors and Affiliations

  • Weiping Liao
    • 1
  • Lei He
    • 1
  1. 1.Electrical Engineering DepartmentUniversity of CaliforniaLos Angeles

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