Abstract
A novel technique for improving the energy efficiency of microprocessors is disclosed. This new method relies on a fault-tolerance mechanism for timing violations, based on a speculative execution technique. Since power reduces quadratically with supply voltage, supply voltage reductions can result in substantial power savings. However, these reductions also cause a longer gate delay, and so the clock frequency must be reduced so that timing constraints of critical paths are not violated. If any fault-tolerance mechanism is provided for timing faults, it is not necessary to maintain the constraints. From these observations, we propose a fault-tolerance technique for timing violations, that efficiently utilizes the speculative execution mechanism and reduces power consumption. We call the technique constructive timing violation. The present study evaluated our proposal regarding this technique using a cycle-by-cycle simulator and determined the technique's efficiency regarding energy consumption.
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Sato, T., Arita, I. (2003). Constructive Timing Violation for Improving Energy Efficiency. In: Benini, L., Kandemir, M., Ramanujam, J. (eds) Compilers and Operating Systems for Low Power. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-9292-5_8
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DOI: https://doi.org/10.1007/978-1-4419-9292-5_8
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