Abstract
Caches are an important part of architectural and compiler low-power strategies by reducing memory accesses and energy per access. In this chapter, we examine efficient utilization of data caches for low power in an adaptive memory hierarchy. We focus on the optimization of data reuse through the static analysis of line size adaptivity. We present an approach that enables the quantification of data misses with respect to cache line size at compile-time. This analysis is implemented in a software package STAMINA. Experimental results demonstrate effectiveness and accuracy of the analytical results compared to alternative simulation based methods.
Supported by AMRM DABT63-98-C-0045
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D’Alberto, P., Nicolau, A., Veidenbaum, A., Gupta, R. (2003). Static Analysis of Parameterized Loop Nests for Energy Efficient Use of Data Caches. In: Benini, L., Kandemir, M., Ramanujam, J. (eds) Compilers and Operating Systems for Low Power. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-9292-5_11
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DOI: https://doi.org/10.1007/978-1-4419-9292-5_11
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