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Introduction

  • Harry Foster
  • Adam Krolnik
  • David Lacey

Abstract

Ensuring functional correctness on RTL designs continues to pose one of the greatest challenges for today’s ASIC and SoC design teams. Rooted in that challenge is the goal to shorten the verification cycle. This requires new design and verification techniques.

Keywords

Intellectual Property Output Port Functional Coverage Verification Tool Implementation Intent 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 2003

Authors and Affiliations

  • Harry Foster
    • 1
  • Adam Krolnik
    • 2
  • David Lacey
    • 3
  1. 1.Verplex Systems, Inc.USA
  2. 2.Verplex Systems, Inc.USA
  3. 3.Hewlett-Packard CompanyUSA

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