Advanced hard mask approach of ICs copper interconnects processes integration

Abstract

When scaling the critical dimensions into nanotechnology, the impact of layout and line edge becomes important. Implementation of Cu and low dielectric constant (low-k) materials in the manufacturing process requires a complete understanding of these process characteristics and the challenges that appear during the hard mask based dual damascene approach. To create highly reliable electrical interconnects, the interfaces between the Cu metal and low-k must be optimized during the lithography, etching, ashing and copper processes. For higher aspect ratios interconnect profiles however this approach leads to increased sidewall roughness and undercut. To suppress problems in the photolithography and etching processes, the balance of the processes integration should be quantitatively and instantaneously controlled to the optimum manufacturing technologies. For copper filling engineering, this study also clearly demonstrated that the influence of liner barrier Ta and Cu seed performance of dual damascene manufacturing processes integration. Processes parameters that needed to be tuned are gas flow ratio, pressure and bias of the etch process. These process characteristics and manufacturing mechanism optimization will also be discussed.