Delay Fault Coverage

  • Mukund Sivaraman
  • Andrzej J. Strojwas

Abstract

It is not feasible to test a circuit for delay faults by applying all possible delay tests (i.e., all possible input sequences). For the purposes of delay testing, it is therefore judicious to select a manageable set of test patterns which test each fabricated chip for the presence of delay faults. If a fabricated chip passes a set of delay tests, the confidence one has in the absence of delay faults in the chip is a measure of the effectiveness of the test set. This notion has typically been quantified in terms of the percentage of all possible delay faults which can be detected by the test set. This quantification has been used as a measure of the delay fault coverage of the test set, and has evolved from the definition of fault coverage for functional failures (e.g., stuck-fault coverage), where the coverage of a test set is defined as the percentage of the total number of faults detectable by the test set. However, this quantification is not a realistic metric for delay fault coverage. This is because the size of a delay fault also determines whether or not a delay failure is observed at a circuit output.

Keywords

Estima 

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Copyright information

© Springer Science+Business Media New York 1998

Authors and Affiliations

  • Mukund Sivaraman
    • 1
  • Andrzej J. Strojwas
    • 1
  1. 1.Carnegie Mellon UniversityPittsburghUSA

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