Abstract
The BiCMOS technology has proven to be an excellent workhorse for telecommunication applications [1]. This is due to its excellent digital and analog capabilities as well as the variety of I/O’s it offers. Consequently, this made the design process, using the BiCMOS technology, a very flexible one. However, lately due to the ever increasing complexity of telecommunication switches, the need has arisen for novel circuits with low on-chip power consumption. This is particularly important in two classes of circuits which conventionally consumed the most power; signal translation circuits, and I/O circuits. Moreover, since the DSP portions of telecommunication chips are usually implemented using CMOS logic, the supply voltages will have to be scaled down for future submicron and deep submicron BiCMOS technologies to maintain a high reliability for the CMOS circuits. Also, many of the recently reported low-voltage-swing driver circuits have a compatibility problem. These circuits range from reduced-swing CMOS [2], and CMOS pseudo-ECL or CMOS 100K ECL [3], [4], to CMOS GTL [5]. While the CMOS reduced-swing transceivers have limited speed, the CMOS true or pseudo ECL are complicated to design and have high power consumption, and the GTL requires different reference and termination voltages. Each of these transceivers as well as the true or pseudo Bipolar ECL or CML transceivers requires a different termination voltage and hence the incompatibility problem arises. This means that signal conversion parts as well as multiple termination and reference voltages would be required in systems using parts with different transceiver types, thus increasing the overall system cost and complexity.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
R. Hadaway, et al., ”BiCMOS Technology for Telecommunications,” IEEE BCTM Proc, pp. 159–166, 1993.
John H. Quigley, et al., ”Current Mode Transceiver Logic (CMTL) for Reduced Swing CMOS, Chip to Chip Communication,” IEEE Int. ASIC Conf. and Exhibit Proc, pp. 452–455, 1993.
M. Pedersen, and P. Metz, et al., ”A CMOS to 100K ECL Interface Circuit,” ISSCC Tech. Dig., pp. 226–227, 1989.
T. J. Gabara and S. Knauer, ”Digital Transistor Sizing Techniques Applied to 100K ECL CMOS Output Buffers,” IEEE Int. ASIC Conf. and Exhibit Proc., pp. 456–459, 1993.
Bill Gunning, et al., ”A CMOS Low-Voltage-Swing Transmission-Line Transceiver,” ISSCC Tech. Dig., pp. 58–59, 1992.
C. T. Chuang, and D. D. Tang, ”High-Speed Low-Power AC-Coupled Complementary Push-Pull ECL Circuit,” IEEE J. Solid-State Circuits, Vol. 27, pp. 660–663, 1992.
C. T. Chuang, et al, ”High-Speed Low-Power ECL Circuit With AC-Coupled Self-Biased Dynamic Current Source and Active-Pull-Down Emitter-Follower Stage,” IEEE J. Solid-State Circuits, Vol. 27, pp. 1207–1210, 1992.
W. Wilhelm, and P. Weger, ”2V Low-Power Bipolar Logic,” ISSCC Tech. Dig., pp. 94–95, 1993.
H. Shin, ”A Self-Biased Feedback-Controlled Pull-Down Emitter Follower for High-Speed Low-Power Bipolar Logic Circuits,” IEEE J. Solid-State Circuits, Vol. 29, pp. 523–528, 1994.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 1997 Springer Science+Business Media New York
About this chapter
Cite this chapter
Elrabaa, M.S., Abu-Khater, I.S., Elmasry, M.I. (1997). Inter-Chip Low-Voltage-Swing Transceivers. In: Advanced Low-Power Digital Circuit Techniques. The Springer International Series in Engineering and Computer Science, vol 405. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-8546-0_7
Download citation
DOI: https://doi.org/10.1007/978-1-4419-8546-0_7
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-4636-4
Online ISBN: 978-1-4419-8546-0
eBook Packages: Springer Book Archive