Low-Power Embedded BiCMOS/ECL SRAMS

Abstract

As was mentioned in chapter 1, one of the most successful applications of BiCMOS technology was in the design of SRAMs [1]. By combining the high-density and low power dissipation of CMOS with the extremely fast speed of bipolar ECL techniques, BiCMOS SRAMs achieved speeds very close to that of bipolar SRAMs at power levels close to that of CMOS SRAMs [2]. BiCMOS ECL SRAMs were usually designed to operate at the maximum power level allowed by still or forced-air cooled plastic packages (600-1000 mW) [3] for maximum speed. With each new generation, the speed was enhanced by scaling the technology and/or using novel circuit techniques and architectures. Hence, the speed was slightly increased, keeping the power consumption at a relatively constant level. This was true for both CMOS and BiCMOS SRAMs. Figure 5.1 shows a comparison of the speed (access time) and power consumption of the latest generations of CMOS and BiCMOS ECL SRAMs. For each generation, the minimum feature size (i.e L _e ff) was approximately the same for both types of SRAMs. This figure shows that the speed of BiCMOS SRAMs increased steadily with each generation while the power remained almost constant. This, however, meant that with each new generation, less power was allocated to the ECL I/Os (which increased by two I/Os with each generation). Hence, the speed advantage of these ECL I/Os decreased with each new generation. Coupled with the fact that it is very difficult to implement automatic address transition detection (ATD) techniques with the ECL address inputs (to reduce the overall power consumption), the development of truly asynchronous 16Mb+ ECL SRAMs was very much hindered. Embedded BiCMOS SRAMs face the same power dilemma as stand-alone SRAMs since the power budget allocated for these SRAMs are usually very small.