Low-Power High-Performance Multipliers

  • Muhammad S. Elrabaa
  • Issam S. Abu-Khater
  • Mohamed I. Elmasry
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 405)


Digital signal processing (DSP) is the technology at the heart of the next generation of personal communication systems. Most DSP systems incorporate a multiplication unit to implement algorithms such as convolution and filtering. In many DSP algorithms, the multiplier lies in the critical delay path and ultimately determines the performance of the algorithm. Figure 3.1 shows an implementation of the discrete cosine transform, an algorithm widely used in image and video compression. This particular implementation requires 32 convolutions and 8 additions [1]. Thus, improving the throughput of this algorithm requires a high-performance multiplier. Traditionally in order to achieve high performance multipliers, parallel addition of the partial products is used along with reducing the technology feature size.


Power Dissipation Partial Product Full Adder Half Adder Multiplier Array 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media New York 1997

Authors and Affiliations

  • Muhammad S. Elrabaa
    • 1
  • Issam S. Abu-Khater
    • 1
  • Mohamed I. Elmasry
    • 2
  1. 1.Intel CorporationUSA
  2. 2.University of WaterlooUSA

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