Low-Power High-Performance Multipliers
Digital signal processing (DSP) is the technology at the heart of the next generation of personal communication systems. Most DSP systems incorporate a multiplication unit to implement algorithms such as convolution and filtering. In many DSP algorithms, the multiplier lies in the critical delay path and ultimately determines the performance of the algorithm. Figure 3.1 shows an implementation of the discrete cosine transform, an algorithm widely used in image and video compression. This particular implementation requires 32 convolutions and 8 additions . Thus, improving the throughput of this algorithm requires a high-performance multiplier. Traditionally in order to achieve high performance multipliers, parallel addition of the partial products is used along with reducing the technology feature size.
KeywordsPower Dissipation Partial Product Full Adder Half Adder Multiplier Array
Unable to display preview. Download preview PDF.
- Nomura et al, ”A 300-MHz 16-b 0.5 μm BiCMOS Digital Signal Processor Core LSI”, IEEE Journal of Solid State Circuits, Vol. 29, No. 3, pp. 290–297.Google Scholar
- K. Hwang, ”Computer Arithmetic: Principles, Architecture, and Design”, John Wiley and Sons, 1979.Google Scholar
- J.J.F. Cavanagh, ”Computer Science Series: Digital Computer Arithmatic”, McGraw-Hill Book Co., 1984.Google Scholar
- Ahmad R. Fridi, ”Partial Multiplication; A Low-Power Approach for Parallel Multiplier”, ECE729 Course Project, Department of Electrical and Computer Engineering, University of Waterloo, April 1994.Google Scholar
- N.H.E. Weste and K. Eshraghian, ”Principles of CMOS VLSI Design: A systems Perspective”, Addison-Wesley Publishing Company, 2nd ED, 1993.Google Scholar