Abstract
In this introductory chapter, a brief description of the power estimation and evaluation for digital circuits is given in the next section. This would serve as a back ground for the subsequent chapters. Also, the impact of the new power-concious design philosophy on the process design and semiconductor technology is outlined. Finally, an overview of the book’s main chapters is provided.
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References
A. Bellaouar and M. I. Elmasry, “Low-Power Digital VLSI Design Circuits and Systems”, Kluwer Academics Publications, MA, 1995.
H. Oyamatsu, K. Kinugawa, and M. Kakumu, “Design Methodology of Deep Submicron CMOS Devices for 1 V Operation,” Symposium on VLSI Technology Tech. Dig., pp. 89–90, 1993.
H. Yoshimura, F. Matsuoka, and M. Kakumu, “New CMOS Shallow Junction Well FET Structure (CMOS-SJET) for Low Power-Supply Voltage,” International Electron Devices Meeting Tech. Dig., pp. 909–912, December 1992.
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© 1997 Springer Science+Business Media New York
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Elrabaa, M.S., Abu-Khater, I.S., Elmasry, M.I. (1997). Low-Power VLSI Design. In: Advanced Low-Power Digital Circuit Techniques. The Springer International Series in Engineering and Computer Science, vol 405. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-8546-0_1
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DOI: https://doi.org/10.1007/978-1-4419-8546-0_1
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-4636-4
Online ISBN: 978-1-4419-8546-0
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