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Long Path-Based Hybrid Method

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Test and Diagnosis for Small-Delay Defects

Abstract

As discussed in the previous chapter, small-delay defects (SDDs) introduce a small amount of extra delay to the design, and it is commonly recommended to detect SDDs via long paths running through fault sites [3, 4, 5, 6, 7, 8, 9, 10]. Therefore, if a pattern sensitizes a large number of long paths, it can detect all the SDDs along these long paths, and can be considered as an effective pattern. That is the basis of the book.

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References

  1. IWLS 2005 Benchmarks, “http://iwls.org/iwls2005/benchmarks.html

  2. Synopsys Inc., “SOLD Y-2007, Vol. 1–3,” Synopsys Inc., 2007

    Google Scholar 

  3. J. Savir and S. Patil, “On Broad-Side Delay Test,” in Proc. VLSI 2 Symp. (VTS’94), pp. 284–290, 1994

    Google Scholar 

  4. R. Mattiuzzo, D. Appello C. Allsup, “Small Delay Defect Testing,” http://www.tmworld.com/article/CA6660051.html Test & Measurement World, 2009

  5. M. E. Amyeen, S. Venkataraman, A. Ojha, S. Lee, “Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor”, IEEE International Test Conference (ITC’04), pp. 669–678, 2004

    Google Scholar 

  6. Y. Huang, “On N-Detect Pattern Set Optimization,” in Proc. IEEE the 7th International Symposium on Quality Electronic Design (ISQED’06), 2006

    Google Scholar 

  7. Mentor Graphics, “Understanding how to run timing-aware ATPG,” Application Note, 2006

    Google Scholar 

  8. P. Gupta, and M. S. Hsiao, “ALAPTF: A new transition fault model and the ATPG algorithm,” in Proc. Int. Test Conf. (ITC’04), pp. 1053–1060, 2004

    Google Scholar 

  9. S. Goel, N. Devta-Prasanna and R. Turakhia, “Effective and Efficient Test pattern Generation for Small Delay Defects,” IEEE VLSI Test Symposium (VTS’09), 2009

    Google Scholar 

  10. W. Qiu, J. Wang, D. Walker, D. Reddy, L. Xiang, L. Zhou, W. Shi, and H. Balachandran, “K Longest Paths Per Gate (KLPG) Test Generation for Scan Scan-Based Sequential Circuits,” in Proc. IEEE ITC, pp. 223–231, 2004

    Google Scholar 

  11. A. K. Majhi, V. D. Agrawal, J. Jacob, L. M. Patnaik, “Line coverage of path delay faults,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 5, pp. 610–614, 2000

    Google Scholar 

  12. H. Lee, S. Natarajan, S. Patil, I. Pomeranz, “Selecting High-Quality Delay Tests for Manufacturing Test and Debug,” in Proc. IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’06), 2006

    Google Scholar 

  13. N. Ahmed, M. Tehranipoor and V. Jayaram, “Timing-Based Delay Test for Screening Small Delay Defects,” IEEE Design Automation Conf., pp. 320–325, 2006

    Google Scholar 

  14. M. Yilmaz, K. Chakrabarty, and M. Tehranipoor, “Test-Pattern Grading and Pattern Selection for Small-Delay Defects,” in Proc. IEEE VLSI Test Symposium (VTS’08), 2008

    Google Scholar 

  15. M. Yilmaz, K. Chakrabarty, and M. Tehranipoor, “Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects,” in Proc. Int. Test Conference (ITC’08), 2008

    Google Scholar 

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Correspondence to Mohammad Tehranipoor .

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© 2011 Springer Science+Business Media, LLC

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Tehranipoor, M., Peng, K., Chakrabarty, K. (2011). Long Path-Based Hybrid Method. In: Test and Diagnosis for Small-Delay Defects. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-8297-1_3

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  • DOI: https://doi.org/10.1007/978-1-4419-8297-1_3

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  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4419-8296-4

  • Online ISBN: 978-1-4419-8297-1

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