Nanoscale Memory Repair pp 19-67 | Cite as

# Redundancy

For designing redundancy circuit, the estimation of the advantages and disadvantages is indispensable. The introduction of redundancy in a memory chip results in yield improvement and fabrication-cost reduction. However, it also causes the following penalties. First, spare memory cells to replace faulty cells, programmable devices to memorize faulty addresses, and control circuitry to increase chip size. Second, the time required for the judgment whether the input address is faulty or not is added to the access time. Third, special process steps to fabricate the programmable devices and test time to store faulty addresses into the devices are required. Therefore, the design of redundancy circuit requires a trade-off between yield improvement and these penalties. The estimation of yield improvement requires a fault-distribution model. There are two representative models, Poisson distribution model and negative-binomial model, which are often used for the yield analysis of memory LSIs. The “replacement” of normal memory elements by spare elements requires checking whether the accessed address includes faulty elements, and if yes, inhibiting the faulty element from being activated and activating a spare element instead. These procedures should be realized with as small penalty as possible. One of the major issues for the replacement is memory-array division. Memory arrays are often divided into subarrays for the sake of access-time reduction, power reduction, and signal/noise ratio enhancement. There are two choices for memories with array division: (1) a faulty element in a subarray is replaced only by a spare element in the same subarray (intrasubarray replacement) and (2) a faulty element in a subarray may be replaced by a spare element in another subarray (intersubarray replacement). The former has smaller access penalty, while the latter realizes higher replacement efficiency. It is also possible that a subarray is replaced by a spare subarray. The devices for memorizing faulty addresses and test for finding out an effective replacement are also important issues for redundancy.

## Keywords

Input Address Replacement Unit Faulty Element Column Address Fuse Block## References

- 1.S. E. Schuster, “Multiple word/bit line redundancy for semiconductor memories,” IEEE J. Solid-State Circuits, vol. SC-13, pp. 698–703, Oct. 1978.CrossRefGoogle Scholar
- 2.T. Mano, M. Wada, N. Ieda and M. Tanimoto, “A redundancy circuit for a fault-tolerant 256K MOS RAM,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 726–731, Aug. 1982.CrossRefGoogle Scholar
- 3.S. Fujii, K. Natori, T. Furuyama, S. Saito, H. Toda, T. Tanaka and O. Ozawa, “A low-power sub 100 ns 256K bit dynamic RAM,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 441–446, Oct. 1983.CrossRefGoogle Scholar
- 4.Y. Nishimura, M. Hamada, H. Hidaka, H. Ozaki and K. Fujishima, “A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode,” IEEE J. Solid-State Circuits, vol. 24, pp. 43–49, Feb. 1989.CrossRefGoogle Scholar
- 5.M. Horiguchi, J. Etoh, M. Aoki, K. Itoh and T. Matsumoto, “A flexible redundancy technique for high-density DRAMs,” IEEE J. Solid-State Circuits, vol. 26, pp. 12–17, Jan. 1991.CrossRefGoogle Scholar
- 6.C. H. Stapper, Jr., “On a composite model to the IC yield problem,” IEEE J. Solid-State Circuits, vol. SC-10, pp. 537–539, Dec. 1975.CrossRefGoogle Scholar
- 7.C. H. Stapper, A. N. McLaren and M. Dreckmann, “Yield model for productivity optimization of VLSI memory chips with redundancy and partially good product,” IBM J. Res. Dev., vol. 24, pp. 398–409, May 1980.CrossRefGoogle Scholar
- 8.T. Okabe, M. Nagata and S. Shimada, “Analysis on yield of integrated circuits and a new representation for the yield,” Trans. IEE J., vol, 92-C, pp. 399–406, Dec. 1972 (in Japanese).Google Scholar
- 9.C. H. Stapper, “Yield model for fault clusters within integrated circuits,” IBM J. Res. Dev., vol. 28, pp. 636–640, Sep. 1984.CrossRefGoogle Scholar
- 10.S. Kikuda, H. Miyamoto, S. Mori, M. Niiro and M. Yamada, “Optimized redundancy selection based on failure-related yield model for 64-Mb DRAM and beyond,” IEEE J. Solid-State Circuits, vol. 26, pp. 1550–1555, Nov. 1991.CrossRefGoogle Scholar
- 11.T. Yamagata, H. Sato, K. Fujita, Y. Nishimura and K. Anami, “A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond,” IEEE J. Solid-State Circuits, vol. 31, pp. 195–201, Feb. 1996.CrossRefGoogle Scholar
- 12.K. Imamiya, J. Miyamoto, N. Ohtsuka, N. Tomita and Y. Iyama, “Statistical memory yield analysis and redundancy design considering fabrication line improvement,” IEICE Trans. Electron., vol. E76-C, pp. 1626–1631, Nov. 1993.Google Scholar
- 13.R. P. Cenker, D. G. Clemons, W. R. Huber, J. B. Petrizzi, F. J. Procyk and G. M. Trout, “A fault-tolerant 64K dynamic random-access memory,” IEEE Trans. Electron Devices, vol. ED-26, pp. 853–860, June 1979.CrossRefGoogle Scholar
- 14.E. A. Reese, D. W. Spaderna, S. T. Flannagan and F. Tsang, “A 4K × 8 dynamic RAM with self-refresh,” IEEE J. Solid-State Circuits, vol. SC-16, pp. 479–487, Oct. 1981.CrossRefGoogle Scholar
- 15.K. Kokkonen, P. O. Sharp, R. Albers, J. P. Dishaw, F. Louie and R. J. Smith, “Redundancy techniques for fast static RAMs,” in ISSCC Dig. Tech. Papers, Feb. 1981, pp. 80–81.Google Scholar
- 16.A. Ohba, S. Ohbayashi, T. Shiomi, S. Takano, K. Anami, H. Honda, Y. Ishigaki, M. Hatanaka, S. Nagao and S. Kayano, “A 7-ns 1-Mb BiCMOS ECL SRAM with shift redundancy,” IEEE J. Solid-State Circuits, vol. 26, pp. 507–512, Apr. 1991.CrossRefGoogle Scholar
- 17.H. Noda, K. Inoue, M. Kuroiwa, A. Amo, A. Hachisuka, H. J. Mattausch, T. Koide, S. Soeda, K. Dosaka and K. Arimoto, “A 143MHz 1.1W 4.5Mb dynamic TCAM with hierarchical searching and shift redundancy architecture,” ISSCC Dig. Tech. Papers, Feb. 2004, pp. 208–209.Google Scholar
- 18.A. Roth, D. Foss, R. McKenzie and D. Perry, “Advanced ternary CAM circuits on 0.13 μm logic process technology,” in Proc. CICC, Oct. 2004, pp. 465–468.Google Scholar
- 19.T. Namekawa, S. Miyano, R. Fukuda, R. Haga, O. Wada, H. Banba, S. Takeda, K. Suda, K. Mimoto, S. Yamaguchi, T. Ohkubo, H. Takato and K. Numata, “Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus,” IEEE J. Solid-State Circuits, vol. 35, pp. 705–712, May 2000.CrossRefGoogle Scholar
- 20.M. Horiguchi, “Redundancy techniques for high-density DRAMs,” in Proc. Int. Conf. on Innovative Systems Silicon, Oct. 1997, pp. 22–29.Google Scholar
- 21.R. Hori, K. Itoh, J. Etoh, S. Asai, N. Hashimoto, K. Yagi and H. Sunami, “An experimental 1 Mbit DRAM based on high S/N design,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 634–640, Oct. 1984.CrossRefGoogle Scholar
- 22.K. Itoh, “Trends in megabit DRAM circuit design,” IEEE J. Solid-State Circuits, vol. 25, pp.778–789, June 1990.CrossRefGoogle Scholar
- 23.K. Itoh,
*VLSI Memory Design*, Baifukan, Tokyo, 1994 (in Japanese), Chapter 2.Google Scholar - 24.K. Itoh,
*VLSI Memory Chip Design*, Springer, NY, 2001, Chapter 3.MATHGoogle Scholar - 25.M. Yoshimoto, K. Anami, H. Shinohara, T. Yoshihara, H. Takagi, S. Nagao, S. Kayano and T. Nakano, “A divided word-line structure in the static RAM and its application to a 64k full CMOS RAM,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 479–485, Oct. 1983.CrossRefGoogle Scholar
- 26.K. Noda, T. Saeki, A. Tsujimoto, T. Murotani and K. Koyama, “A boosted dual word-line decoding scheme for 256Mb DRAMs,” in Symp. VLSI Circuits Dig. Tech. Papers, June 1992, pp. 112–113.Google Scholar
- 27.D. Galbi, K. Althoff, R. Parent, O. Kiehl, R. Houghton, F. Bonner, M. Killian, A. Wilson, K. Lau, M. Clinton, D. Chapman and H. Fischer, “A 33-ns 64-Mbit DRAM with master-wordline architecture,” in Proc. ESSCIRC, Sep. 1992, pp. 131–134.Google Scholar
- 28.K. Furutani, T. Hamamoto, T. Miki, M. Nakano, T. Kono, S. Kikuda, Y. Konishi and T. Yoshihara, “Highly flexible row and column redundancy and cycle time adaptive read data path for double data rate synchronous memories,” IEICE Trans. Electron., vol. E88-C, pp. 255–263, Feb. 2005.CrossRefGoogle Scholar
- 29.Y. Takai, M. Fujita, K. Nagata, S. Isa, S. Nakazawa, A. Hirobe, H. Ohkubo, M. Sakao, S. Horiba, T. Fukase, Y. Takaishi, M. Matsuo, M. Komuro, T. Uchida, T. Sakoh, K. Saino, S. Uchiyama, Y. Takada, J. Sekine, N. Nakanishi, T. Oikawa, M. Igeta, H. Tanabe, H. Miyamoto, T. Hashimoto, H. Yamaguchi, K. Koyama, Y. Kobayashi and T. Okuda, “A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme,” IEEE J. Solid-State Circuits, vol. 35, pp. 149–162, Feb. 2000.CrossRefGoogle Scholar
- 30.H. Yahata, Y. Okuda, H. Miyashita, H. Chigasaki, B. Taruishi, T. Akiba, Y. Kawase, T. Tachibana, S. Ueda, S. Aoyama, A. Tsukimori, K. Shibata, M. Horiguchi, Y. Saiki and Y. Nakagome, “A 256-Mb double-data-rate SDRAM with a 10-mW analog DLL circuit,” in Symp. VLSI Circuits Dig. Tech. Papers, June 2000, pp. 74–75.Google Scholar
- 31.K. Sasaki, K. Ishibashi, T. Yamanaka, N. Hashimoto, T. Nishida, K. Shimohigashi, S. Hanamura and S. Honjo, “A 9-ns 1-Mbit CMOS SRAM,” IEEE J. Solid-State Circuits, vol. 24, pp. 1219–1225, Oct. 1989.CrossRefGoogle Scholar
- 32.H. Yamauchi, T. Suzuki, A. Sawada, T. Iwata, T. Tsuji, M. Agata, T. Taniguchi, Y. Odake, K. Sawada, T. Ohnishi, M. Fukumoto, T. Fujita and M. Inoue, “A circuit technology for high-speed battery-operated 16-Mb CMOS DRAM’s,” IEEE J. Solid-State Circuits, vol. 28, pp. 1084–1091, Nov. 1993.CrossRefGoogle Scholar
- 33.Y. Yokoyama, N. Itoh, M. Katayama, M. Hasegawa, K. Takashima, H. Akasaki, M. Kaneda, T. Ueda, Y. Tanaka, E. Yamasaki, M. Todokoro, K. Toriyama, H. Miki, M. Yagyu, T. Kobayashi, S. Miyaoka and N. Tamba, “A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%,” IEEE J. Solid-State Circuits, vol. 36, pp. 503–509, Mar. 2001.CrossRefGoogle Scholar
- 34.K. Ishibashi, K. Komiyaji, S. Morita, T. Aoto, S. Ikeda, K. Asayama, A. Koike, T. Yamanaka, N. Hashimoto, H. Iida, F. Kojima, K. Motohashi and K. Sasaki, “A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers,” IEEE J. Solid-State Circuits, vol. 29, pp. 411–418, Apr. 1994.CrossRefGoogle Scholar
- 35.M. Asakura, T. Oishi, S. Tomishima, H. Hidaka, K. Arimoto and K. Fujishima, “A hierarchical bit-line architecture with flexible redundancy and block compare test for 256Mb DRAM,” in Symp. VLSI Circuits Dig. Tech. Papers, May 1993, pp. 93–94.Google Scholar
- 36.T. Kirihata, Y. Watanabe, H. Wong, J. K. DeBrosse, M. Yoshida, D. Katoh, S. Fujii, M. R. Wordeman, P. Poechmueller, S. A. Parke and Y. Asao, “Fault-tolerant designs for 256 Mb DRAM,” IEEE J. Solid-State Circuits, vol. 31, pp. 558–566, Apr. 1996.CrossRefGoogle Scholar
- 37.G. Kitsukawa, M. Horiguchi, Y. Kawajiri, T. Kawahara, T. Akiba, Y. Kawase, T. Tachibana, T. Sakai, M. Aoki, S. Shukuri, K. Sagara, R. Nagai, Y. Ohji, N. Hasegawa, N. Yokoyama, T. Kisu, H. Yamashita, T. Kure and T. Nishida, “256-Mb DRAM circuit technologies for file applications,” IEEE J. Solid-State Circuits, vol. 28, pp. 1105–1113, Nov. 1993.CrossRefGoogle Scholar
- 38.K. Furutani, T. Ooishi, M. Asakura, H. Hidaka, H. Ozaki and M. Yamada, “A board level parallel test circuit and a short circuit failure repair circuit for high-density, low-power DRAMs,” IEICE Trans. Electron., vol. E80-C, pp. 582–589, Apr. 1997.Google Scholar
- 39.M. Asakura, T. Ohishi, M. Tsukude, S. Tomishima, H. Hidaka, K. Arimoto, K. Fujishima, T. Eimori, Y. Ohno, T. Nishimura, M. Yasunaga, T. Kondoh, S. Satoh, T. Yoshihara and K. Demizu, “A 34ns 256Mb DRAM with boosted sense-ground scheme,” in ISSCC Dig. Tech. Papers, Feb. 1994, pp. 140–141.Google Scholar
- 40.K. Lim, S. Kang, J. Choi, J. Joo, Y. Lee, J. Lee S. Cho and B. Ryu, “Bit line coupling scheme and electrical fuse circuit for repairable operation of high density DRAM,” Symp. VLSI Circuits Dig. Tech. Papers, June 2001, pp. 33–34.Google Scholar
- 41.K. H. Kyung, C. W. Kim, J. Y. Lee, J. H. Kook, S. M. Seo, D. Y. Kim, J. H. Kim, J. Sunwoo, H. C. Lee, C. S. Kim, B. H. Jeong, Y. S. Sohn, S. P. Hong, J. H. Lee, J. H. Yoo and S. I. Cho, “A 800Mb/s/pin 2Gb DDR2 SDRAM with an 80nm triple metal technology,” ISSCC Dig. Tech. Papers, Feb. 2005, pp. 468–469.Google Scholar
- 42.K. Shimohigashi, M. Ishihara and S. Shimizu, “Redundancy techniques for dynamic RAMs,” Jpn. J. Appl. Phys., vol. 22, pp. 63–67, Apr. 1983.Google Scholar
- 43.S. Ohbayashi, M. Yabuuchi, K. Kono, Y. Oda, S. Imaoka, K. Usui, T. Yonezu, T. Iwamoto, K. Nii, Y. Tsukamoto, M. Arakawa, T. Uchida, M. Okada, A. Ishii, T. Yoshihara, H. Makino, K. Ishibashi and H. Shinohara, “A 65nm embedded SRAM with wafer level burn-in mode, leak-bit redundancy and Cu e-trim fuse for known good die,” IEEE J. Solid-State Circuits, vol. 43, pp. 96–108, Jan. 2008.CrossRefGoogle Scholar
- 44.T. Mano, K. Takeya, T. Watanabe, N. Ieda, K. Kiuchi, E. Arai, T. Ogawa and K. Hirata, “A fault-tolerant 256K RAM fabricated with molybdenum-polysilicon technology,” IEEE J. Solid-State Circuits, vol. SC-15, pp. 865–872, Oct. 1980.CrossRefGoogle Scholar
- 45.O. Minato, T. Masuhara, T. Sasaki, Y. Sakai, T. Hayashida, K. Nagasawa, K. Nishimura and T. Yasui, “A Hi-CMOSII 8K × 8 bit static RAM,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 793–798, Oct. 1982.CrossRefGoogle Scholar
- 46.J.-K. Wee, W. Yang, E.-K. Ryou, J.-S. Choi, S.-H. Ahn, J.-Y. Chung and S.-C. Kim, “An antifuse EPROM circuitry scheme for field-programmable repair in DRAM,” IEEE J. Solid-State Circuits, vol. 35, pp. 1408–1414, Oct. 2000.CrossRefGoogle Scholar
- 47.J.-K. Wee, K.-S. Min, J.-T. Park, S.-P. Lee, Y.-H. Kim, T.-H. Yang, J.-D. Joo and J.-Y. Chung, “A post-package bit-repair scheme using static latches with bipolar-voltage programming antifuse circuit for high-density DRAMs,” IEEE J. Solid-State Circuits, vol. 37, pp. 251–254, Feb. 2002.CrossRefGoogle Scholar
- 48.E. M. Lucero, N. Challa and J. Fields Jr., “A 16 kbit smart 5 V-only EEPROM with redundancy,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 539–544, Oct. 1983.CrossRefGoogle Scholar
- 49.S. Shukuri, K. Yanagisawa and K. Ishibashi, “CMOS process compatible ie-flash (inverse gate electrode flash) technology for system-on-a chip,” IEICE Trans. Electron., vol. E84-C, pp. 734–739, June 2001.Google Scholar
- 50.M. Yamaoka, K. Yanagisawa, S. Shukuri, K. Norisue and K. Ishibashi, “A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit,” IEEE J. Solid-State Circuits, vol. 37, pp. 599–604, May 2002.CrossRefGoogle Scholar
- 51.M. Tarr, D. Boudreau and R. Murphy, “Defect analysis system speeds test and repair of redundant memories,” Electronics, vol. 57, pp. 175–179, Jan. 1984.Google Scholar
- 52.J. R. Day, “A fault-driven, comprehensive redundancy algorithm,” IEEE Design Test Comput., vol. 2, pp. 35–44, June 1985.CrossRefGoogle Scholar
- 53.W. K. Huang, Y.-N. Shen and F. Lombardi, “New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement,” IEEE Trans. Comput. Aided Des., vol. 9, pp. 323–328, Mar. 1990.CrossRefGoogle Scholar
- 54.T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada and H. Hidaka, “A built-in self-repair analyzer (CRESTA) for embedded DRAMs,” in Proc. ITC, Oct. 2000, pp. 567–574.Google Scholar
- 55.C.-T. Huang, C.-F. Wu, J.-F. Li and C.-W. Wu, “Built-in redundancy analysis for memory yield improvement,” IEEE Trans. Reliab., vol. 52, pp. 386–399, Dec. 2003.CrossRefGoogle Scholar
- 56.N. Ohtsuka, S. Tanaka, J. Miyamoto, S. Saito, S. Atsumi, K. Imamiya, K. Yoshikawa, N. Matsukawa, S. Mori, N. Arai, T. Shinagawa, Y. Kaneko, J. Matsunaga and T. Iizuka, “A 4-Mbit CMOS EPROM,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 669–675, Oct. 1987.CrossRefGoogle Scholar
- 57.D. Kantz, J. R. Goetz, R. Bender, M. Baehring, J. Wawersig, W. Meyer and W. Mueller, “A 256K DRAM with descrambled redundancy test capability,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 596–602, Oct. 1984.CrossRefGoogle Scholar