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Imperfection-Immune Carbon Nanotube VLSI Circuits

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Nanoelectronic Circuit Design

Abstract

Carbon Nanotube Field Effect Transistors (CNFETs), consisting of semiconducting single walled Carbon Nanotubes (CNTs), show great promise as extensions to silicon CMOS. While there has been significant progress at a single-device level, a major gap exists between such results and their transformation into VLSI CNFET technologies. Major CNFET technology challenges include mis-positioned CNTs, metallic CNTs, and wafer-scale integration. This work presents design and processing techniques to overcome these challenges. Experimental results demonstrate the effectiveness of the presented techniques.

Mis-positioned CNTs can result in incorrect logic functionality of CNFET circuits. A new layout design technique produces CNFET circuits implementing arbitrary logic functions that are immune to a large number of mis-positioned CNTs. This technique is significantly more efficient compared to traditional defect- and fault-tolerance. Furthermore, it is VLSI-compatible and does not require changes to existing VLSI design and manufacturing flows.

A CNT can be semiconducting or metallic depending upon the arrangement of carbon atoms. Typical CNT synthesis techniques yield ~33% metallic CNTs. Metallic CNTs create source-drain shorts in CNFETs resulting in excessive leakage (Ion/Ioff< 5) and highly degraded noise margins. A new technique, VLSI-compatible Metallic-CNT Removal (VMR), overcomes metallic CNT challenges by combining layout design with CNFET processing. VMR produces CNFET circuits with Ion/Ioff in the range of 103-105, and overcomes the limitations of existing metallic-CNT removal techniques.

We also present the first experimental demonstration of VLSI-compatible CNFET combinational circuits (e.g., computational elements such as half-adder sum-generators) and storage circuits (e.g., sequential elements such as D-latches) that are immune to inherent CNT imperfections. These experimentally-demonstrated circuits form essential building blocks for large-scale digital computing systems.

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Notes

  1. 1.

    CNT density of >100 CNTs/µm is needed for CNFETs to be competitive with silicon CMOS [Deng 07, Patil 09a].

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Authors and Affiliations

  1. Department of Electrical Engineering, Stanford University, Stanford, CA, 94305, USA

    Nishant Patil

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  1. Nishant Patil
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  2. Albert Lin
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  3. Jie Zhang
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  4. Hai Wei
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  5. H.-S. Philip Wong
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  6. Subhasish Mitra
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Correspondence to Nishant Patil .

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Editors and Affiliations

  1. Dept. Electrical Engineering, Princeton University, Olden Street, Princeton, 08544, New Jersey, USA

    Niraj K. Jha

  2. Dept. Electrical & Computer Engineering, University of Illinois, Urbana-Champaign, W. Main St. 1308, Urbana, 61801, Illinois, USA

    Deming Chen

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Patil, N., Lin, A., Zhang, J., Wei, H., Wong, HS.P., Mitra, S. (2011). Imperfection-Immune Carbon Nanotube VLSI Circuits. In: Jha, N., Chen, D. (eds) Nanoelectronic Circuit Design. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-7609-3_8

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  • DOI: https://doi.org/10.1007/978-1-4419-7609-3_8

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